@@ -51,37 +51,46 @@ public final class AArch64HotSpotZCompareAndSwapOp extends AArch64AtomicMove.Com
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private final boolean isLogic ;
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private final GraalHotSpotVMConfig config ;
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private final ForeignCallLinkage callTarget ;
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- @ Temp protected AllocatableValue tmp ;
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+ @ Temp private AllocatableValue tmp ;
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+ @ Temp private AllocatableValue tmp2 ;
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- public AArch64HotSpotZCompareAndSwapOp (boolean isLogic , AArch64Kind accessKind , MemoryOrderMode memoryOrder , boolean setConditionFlags , AllocatableValue result , Value expectedValue ,
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+ public AArch64HotSpotZCompareAndSwapOp (boolean isLogic ,
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+ AArch64Kind accessKind ,
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+ MemoryOrderMode memoryOrder ,
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+ boolean setConditionFlags ,
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+ AllocatableValue result ,
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+ Value expectedValue ,
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AllocatableValue newValue ,
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- AllocatableValue addressValue , GraalHotSpotVMConfig config , ForeignCallLinkage callTarget , AllocatableValue tmp ) {
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+ AllocatableValue addressValue ,
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+ GraalHotSpotVMConfig config ,
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+ ForeignCallLinkage callTarget ,
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+ AllocatableValue tmp , AllocatableValue tmp2 ) {
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super (TYPE , accessKind , memoryOrder , setConditionFlags , result , expectedValue , newValue , addressValue );
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this .isLogic = isLogic ;
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this .config = config ;
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this .callTarget = callTarget ;
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this .tmp = tmp ;
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+ this .tmp2 = tmp2 ;
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}
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@ Override
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public void emitCode (CompilationResultBuilder crb , AArch64MacroAssembler masm ) {
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// Use ANY_SIZE here because the store barrier performs 16 and 64 access for atomics.
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AArch64Address location = AArch64Address .createBaseRegisterOnlyAddress (AArch64Address .ANY_SIZE , asRegister (addressValue ));
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- AArch64HotSpotZBarrierSetLIRGenerator .emitStoreBarrier (crb , masm , this , config , location , asRegister (tmp ), ZWriteBarrierSetLIRGeneratorTool .StoreKind .Atomic ,
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+ Register tmpRegister = asRegister (tmp );
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+ AArch64HotSpotZBarrierSetLIRGenerator .emitStoreBarrier (crb , masm , this , config , location , tmpRegister , ZWriteBarrierSetLIRGeneratorTool .StoreKind .Atomic ,
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callTarget , null );
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- try (AArch64MacroAssembler .ScratchRegister sc1 = masm .getScratchRegister ()) {
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- Register rscratch1 = sc1 .getRegister ();
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- // Color newValue and expectedValue into a temporary registers
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- AArch64HotSpotZBarrierSetLIRGenerator .zColor (crb , masm , config , asRegister (tmp ), asRegister (newValue ));
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- AArch64HotSpotZBarrierSetLIRGenerator .zColor (crb , masm , config , rscratch1 , asRegister (expectedValue ));
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- Register address = asRegister (addressValue );
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- // Produce the colored result into a temporary register
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- Register result = asRegister (resultValue );
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- Register expected = rscratch1 ;
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- emitCompareAndSwap (masm , accessKind , address , result , expected , asRegister (tmp ), memoryOrder , setConditionFlags );
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- if (!isLogic ) {
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- AArch64HotSpotZBarrierSetLIRGenerator .zUncolor (masm , config , asRegister (resultValue ));
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- }
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+ Register tmp2Register = asRegister (tmp2 );
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+ // Color newValue and expectedValue into a temporary registers
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+ AArch64HotSpotZBarrierSetLIRGenerator .zColor (crb , masm , config , tmpRegister , asRegister (newValue ));
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+ AArch64HotSpotZBarrierSetLIRGenerator .zColor (crb , masm , config , tmp2Register , asRegister (expectedValue ));
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+ Register address = asRegister (addressValue );
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+ // Produce the colored result into a temporary register
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+ Register result = asRegister (resultValue );
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+ Register expected = tmp2Register ;
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+ emitCompareAndSwap (masm , accessKind , address , result , expected , tmpRegister , memoryOrder , setConditionFlags );
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+ if (!isLogic ) {
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+ AArch64HotSpotZBarrierSetLIRGenerator .zUncolor (masm , config , asRegister (resultValue ));
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}
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}
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}
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