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‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/asm/amd64/AMD64Assembler.java‎

Lines changed: 25 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1525,12 +1525,26 @@ protected final void emitVexOrEvex(AMD64Assembler asm, Register dst, Register nd
15251525
protected final void emitVexOrEvex(AMD64Assembler asm, Register dst, Register nds, AMD64Address src, Register opmask, AVXSize size, int actualPP, int actualMMMMM, int actualW,
15261526
int actualWEvex, int z, int b) {
15271527
asm.interceptMemorySrcOperands(src);
1528+
emitVexOrEvexImpl(asm, dst, nds, src, opmask, size, actualPP, actualMMMMM, actualW, actualWEvex, z, b);
1529+
}
1530+
1531+
protected final void emitVexOrEvex(AMD64Assembler asm, AMD64Address dst, Register nds, Register src, AVXSize size, int actualPP, int actualMMMMM, int actualW, int actualWEvex) {
1532+
emitVexOrEvex(asm, dst, nds, src, Register.None, size, actualPP, actualMMMMM, actualW, actualWEvex, Z0, B0);
1533+
}
1534+
1535+
protected final void emitVexOrEvex(AMD64Assembler asm, AMD64Address dst, Register nds, Register src, Register opmask, AVXSize size, int actualPP, int actualMMMMM, int actualW,
1536+
int actualWEvex, int z, int b) {
1537+
emitVexOrEvexImpl(asm, src, nds, dst, opmask, size, actualPP, actualMMMMM, actualW, actualWEvex, z, b);
1538+
}
1539+
1540+
private void emitVexOrEvexImpl(AMD64Assembler asm, Register reg1, Register reg2, AMD64Address addr, Register opmask, AVXSize size, int actualPP, int actualMMMMM, int actualW,
1541+
int actualWEvex, int z, int b) {
15281542
if (isEvex) {
1529-
checkEvex(asm, size, dst, opmask, z, nds, null, b);
1530-
asm.evexPrefix(dst, opmask, nds, src, size, actualPP, actualMMMMM, actualWEvex, z, b);
1543+
checkEvex(asm, size, reg1, opmask, z, reg2, null, b);
1544+
asm.evexPrefix(reg1, opmask, reg2, addr, size, actualPP, actualMMMMM, actualWEvex, z, b);
15311545
} else {
1532-
checkVex(asm, size, dst, opmask, z, nds, null, b);
1533-
asm.emitVEX(getLFlag(size), actualPP, actualMMMMM, actualW, getRXB(dst, src), nds.isValid() ? nds.encoding() : 0);
1546+
checkVex(asm, size, reg1, opmask, z, reg2, null, b);
1547+
asm.emitVEX(getLFlag(size), actualPP, actualMMMMM, actualW, getRXB(reg1, addr), reg2.isValid() ? reg2.encoding() : 0);
15341548
}
15351549
}
15361550

@@ -1846,13 +1860,13 @@ public VexMoveOp encoding(AMD64SIMDInstructionEncoding encoding) {
18461860

18471861
@Override
18481862
public void emit(AMD64Assembler asm, AVXSize size, AMD64Address dst, Register src) {
1849-
emitVexOrEvex(asm, src, Register.None, dst, size, pp, mmmmm, w, wEvex);
1863+
emitVexOrEvex(asm, dst, Register.None, src, size, pp, mmmmm, w, wEvex);
18501864
asm.emitByte(opReverse);
18511865
asm.emitOperandHelper(src, dst, 0, getDisp8Scale(isEvex, size));
18521866
}
18531867

18541868
public void emit(AMD64Assembler asm, AVXKind.AVXSize size, AMD64Address dst, Register src, Register mask) {
1855-
emitVexOrEvex(asm, src, Register.None, dst, mask, size, pp, mmmmm, w, wEvex, Z0, B0);
1869+
emitVexOrEvex(asm, dst, Register.None, src, mask, size, pp, mmmmm, w, wEvex, Z0, B0);
18561870
asm.emitByte(opReverse);
18571871
asm.emitOperandHelper(src, dst, 0, getDisp8Scale(isEvex, size));
18581872
}
@@ -1879,7 +1893,7 @@ public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, R
18791893
}
18801894

18811895
public void emit(AMD64Assembler asm, AVXSize size, AMD64Address dst, Register src, Register mask, int z, int b) {
1882-
emitVexOrEvex(asm, src, Register.None, dst, mask, size, pp, mmmmm, w, wEvex, z, b);
1896+
emitVexOrEvex(asm, dst, Register.None, src, mask, size, pp, mmmmm, w, wEvex, z, b);
18831897
asm.emitByte(opReverse);
18841898
asm.emitOperandHelper(src, dst, 0, getDisp8Scale(isEvex, size));
18851899
}
@@ -2781,7 +2795,7 @@ public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src) {
27812795

27822796
@Override
27832797
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, Register mask, int z, int b) {
2784-
emitVexOrEvex(asm, null, dst, src, mask, AVXSize.XMM, pp, mmmmm, size == AVXSize.DWORD ? VEXPrefixConfig.W0 : VEXPrefixConfig.W1, wEvex, z, b);
2798+
emitVexOrEvex(asm, (Register) null, dst, src, mask, AVXSize.XMM, pp, mmmmm, size == AVXSize.DWORD ? VEXPrefixConfig.W0 : VEXPrefixConfig.W1, wEvex, z, b);
27852799
asm.emitByte(op);
27862800
asm.emitModRM(ext, src);
27872801
}
@@ -2859,7 +2873,7 @@ public VexShiftOp encoding(AMD64SIMDInstructionEncoding encoding) {
28592873

28602874
@Override
28612875
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, int imm8) {
2862-
emitVexOrEvex(asm, null, dst, src, size, pp, mmmmm, w, wEvex);
2876+
emitVexOrEvex(asm, (Register) null, dst, src, size, pp, mmmmm, w, wEvex);
28632877
asm.emitByte(immOp);
28642878
asm.emitModRM(r, src);
28652879
asm.emitByte(imm8);
@@ -2901,7 +2915,7 @@ public VexShiftImmOp encoding(AMD64SIMDInstructionEncoding encoding) {
29012915

29022916
@Override
29032917
public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register src, int imm8) {
2904-
emitVexOrEvex(asm, null, dst, src, size, pp, mmmmm, w, wEvex);
2918+
emitVexOrEvex(asm, (Register) null, dst, src, size, pp, mmmmm, w, wEvex);
29052919
asm.emitByte(op);
29062920
asm.emitModRM(r, src);
29072921
asm.emitByte(imm8);
@@ -2938,7 +2952,7 @@ public void emit(AMD64Assembler asm, AVXSize size, Register dst, Register mask,
29382952
}
29392953

29402954
public void emit(AMD64Assembler asm, AVXSize size, AMD64Address dst, Register mask, Register src) {
2941-
emitVexOrEvex(asm, src, mask, dst, size, pp, mmmmm, w, wEvex);
2955+
emitVexOrEvex(asm, dst, mask, src, size, pp, mmmmm, w, wEvex);
29422956
asm.emitByte(opReverse);
29432957
asm.emitOperandHelper(src, dst, 0, getDisp8Scale(isEvex, size));
29442958
}

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/lir/alloc/SaveCalleeSaveRegisters.java‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,6 @@
3333
import jdk.graal.compiler.lir.LIRInsertionBuffer;
3434
import jdk.graal.compiler.lir.LIRInstruction;
3535
import jdk.graal.compiler.lir.StandardOp;
36-
import jdk.graal.compiler.lir.Variable;
3736
import jdk.graal.compiler.lir.gen.LIRGenerationResult;
3837
import jdk.graal.compiler.lir.gen.LIRGeneratorTool;
3938
import jdk.graal.compiler.lir.gen.MoveFactory;
@@ -43,6 +42,7 @@
4342
import jdk.vm.ci.code.Register;
4443
import jdk.vm.ci.code.RegisterValue;
4544
import jdk.vm.ci.code.TargetDescription;
45+
import jdk.vm.ci.meta.AllocatableValue;
4646
import jdk.vm.ci.meta.PlatformKind;
4747

4848
public class SaveCalleeSaveRegisters extends PreAllocationOptimizationPhase {
@@ -54,7 +54,7 @@ protected void run(TargetDescription target, LIRGenerationResult lirGenRes, PreA
5454
return;
5555
}
5656
LIR lir = lirGenRes.getLIR();
57-
RegisterMap<Variable> savedRegisters = saveAtEntry(lir, context.lirGen, lirGenRes, calleeSaveRegisters, target.arch);
57+
RegisterMap<AllocatableValue> savedRegisters = saveAtEntry(lir, context.lirGen, lirGenRes, calleeSaveRegisters, target.arch);
5858

5959
for (int blockId : lir.getBlocks()) {
6060
if (LIR.isBlockDeleted(blockId)) {
@@ -67,7 +67,7 @@ protected void run(TargetDescription target, LIRGenerationResult lirGenRes, PreA
6767
}
6868
}
6969

70-
private static RegisterMap<Variable> saveAtEntry(LIR lir, LIRGeneratorTool lirGen, LIRGenerationResult lirGenRes, List<Register> calleeSaveRegisters, Architecture arch) {
70+
private static RegisterMap<AllocatableValue> saveAtEntry(LIR lir, LIRGeneratorTool lirGen, LIRGenerationResult lirGenRes, List<Register> calleeSaveRegisters, Architecture arch) {
7171
BasicBlock<?> startBlock = lir.getControlFlowGraph().getStartBlock();
7272
ArrayList<LIRInstruction> instructions = lir.getLIRforBlock(startBlock);
7373
int insertionIndex = lirGenRes.getFirstInsertPosition();
@@ -76,12 +76,15 @@ private static RegisterMap<Variable> saveAtEntry(LIR lir, LIRGeneratorTool lirGe
7676
StandardOp.LabelOp entry = (StandardOp.LabelOp) instructions.get(insertionIndex - 1);
7777
RegisterValue[] savedRegisterValues = new RegisterValue[calleeSaveRegisters.size()];
7878
int savedRegisterValueIndex = 0;
79-
RegisterMap<Variable> saveMap = new RegisterMap<>(arch);
79+
List<Register> allocatables = lirGenRes.getRegisterConfig().getAllocatableRegisters();
80+
RegisterMap<AllocatableValue> saveMap = new RegisterMap<>(arch);
8081
for (Register register : calleeSaveRegisters) {
81-
PlatformKind registerPlatformKind = arch.getLargestStorableKind(register.getRegisterCategory());
82+
PlatformKind registerPlatformKind = lirGenRes.getRegisterConfig().getCalleeSaveRegisterStorageKind(arch, register);
8283
LIRKind lirKind = LIRKind.value(registerPlatformKind);
8384
RegisterValue registerValue = register.asValue(lirKind);
84-
Variable saveVariable = lirGen.newVariable(lirKind);
85+
// Force a non-allocatable register to be saved to a stack slot
86+
// so as to avoid unnecessary register pressure.
87+
AllocatableValue saveVariable = allocatables.contains(registerValue.getRegister()) ? lirGen.newVariable(lirKind) : lirGenRes.getFrameMapBuilder().allocateSpillSlot(lirKind);
8588
LIRInstruction save = lirGen.getSpillMoveFactory().createMove(saveVariable, registerValue);
8689
buffer.append(insertionIndex, save);
8790
save.setComment(lirGenRes, "SaveCalleeSavedRegisters: saveAtEntry");
@@ -93,14 +96,14 @@ private static RegisterMap<Variable> saveAtEntry(LIR lir, LIRGeneratorTool lirGe
9396
return saveMap;
9497
}
9598

96-
private static void restoreAtExit(LIR lir, MoveFactory moveFactory, LIRGenerationResult lirGenRes, RegisterMap<Variable> calleeSaveRegisters, BasicBlock<?> block) {
99+
private static void restoreAtExit(LIR lir, MoveFactory moveFactory, LIRGenerationResult lirGenRes, RegisterMap<AllocatableValue> calleeSaveRegisters, BasicBlock<?> block) {
97100
ArrayList<LIRInstruction> instructions = lir.getLIRforBlock(block);
98101
int insertionIndex = instructions.size() - 1;
99102
LIRInsertionBuffer buffer = new LIRInsertionBuffer();
100103
buffer.init(instructions);
101104
LIRInstruction lirInstruction = instructions.get(insertionIndex);
102105
assert lirInstruction instanceof StandardOp.BlockEndOp : lirInstruction;
103-
calleeSaveRegisters.forEach((Register register, Variable saved) -> {
106+
calleeSaveRegisters.forEach((Register register, AllocatableValue saved) -> {
104107
LIRInstruction restore = moveFactory.createMove(register.asValue(saved.getValueKind()), saved);
105108
buffer.append(insertionIndex, restore);
106109
restore.setComment(lirGenRes, "SaveCalleeSavedRegisters: restoreAtExit");

‎compiler/src/jdk.graal.compiler/src/jdk/graal/compiler/nodes/gc/ZBarrierSet.java‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -184,22 +184,25 @@ public void verifyBarriers(StructuredGraph graph) {
184184
node instanceof LoweredAtomicReadAndWriteNode) {
185185
LIRLowerableAccess read = (LIRLowerableAccess) node;
186186
Stamp stamp = read.getAccessStamp(NodeView.DEFAULT);
187+
BarrierType barrierType = read.getBarrierType();
187188
if (!stamp.isObjectStamp()) {
188-
GraalError.guarantee(read.getBarrierType() == BarrierType.NONE, "no barriers for primitive reads: %s", read);
189+
GraalError.guarantee(barrierType == BarrierType.NONE, "no barriers for primitive reads: %s", read);
189190
continue;
190191
}
191192

192-
BarrierType expectedBarrier = barrierForLocation(read.getBarrierType(), read.getLocationIdentity(), JavaKind.Object);
193+
BarrierType expectedBarrier = barrierForLocation(barrierType, read.getLocationIdentity(), JavaKind.Object);
193194
if (expectedBarrier != null) {
194-
GraalError.guarantee(expectedBarrier == read.getBarrierType(), "expected %s but found %s in %s", expectedBarrier, read.getBarrierType(), read);
195+
GraalError.guarantee(expectedBarrier == barrierType, "expected %s but found %s in %s", expectedBarrier, barrierType, read);
195196
continue;
196197
}
197198

198199
ValueNode base = read.getAddress().getBase();
199200
if (!base.stamp(NodeView.DEFAULT).isObjectStamp()) {
200-
GraalError.guarantee(read.getBarrierType() == BarrierType.NONE, "no barrier for non-heap read: %s", read);
201+
GraalError.guarantee(barrierType == BarrierType.NONE, "no barrier for non-heap read: %s", read);
202+
} else if (node instanceof AbstractCompareAndSwapNode || node instanceof LoweredAtomicReadAndWriteNode) {
203+
GraalError.guarantee(barrierType == BarrierType.FIELD || barrierType == BarrierType.ARRAY, "missing barriers for heap read: %s", read);
201204
} else {
202-
GraalError.guarantee(read.getBarrierType() == BarrierType.READ, "missing barriers for heap read: %s", read);
205+
GraalError.guarantee(barrierType == BarrierType.READ, "missing barriers for heap read: %s", read);
203206
}
204207
} else if (node instanceof AddressableMemoryAccess) {
205208
AddressableMemoryAccess access = (AddressableMemoryAccess) node;

‎regex/src/com.oracle.truffle.regex.test/src/com/oracle/truffle/regex/tregex/TBitSetTest.java‎

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2018, 2021, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2018, 2025, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* The Universal Permissive License (UPL), Version 1.0
@@ -250,6 +250,23 @@ public void testSubtract() {
250250
reset();
251251
}
252252

253+
@Test
254+
public void testEquals() {
255+
TBitSet small = new TBitSet(128);
256+
TBitSet large = new TBitSet(256);
257+
Assert.assertTrue(small.equals(large));
258+
Assert.assertTrue(large.equals(small));
259+
small.set(42);
260+
Assert.assertFalse(small.equals(large));
261+
Assert.assertFalse(large.equals(small));
262+
large.set(42);
263+
Assert.assertTrue(small.equals(large));
264+
Assert.assertTrue(large.equals(small));
265+
large.set(211);
266+
Assert.assertFalse(small.equals(large));
267+
Assert.assertFalse(large.equals(small));
268+
}
269+
253270
private void checkSet(int i) {
254271
oracle.set(i);
255272
bitSet.set(i);

‎regex/src/com.oracle.truffle.regex/src/com/oracle/truffle/regex/util/BitSets.java‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, 2024, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2020, 2025, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* The Universal Permissive License (UPL), Version 1.0
@@ -260,12 +260,12 @@ public static boolean equals(long[] bs1, long[] bs2) {
260260
}
261261
}
262262
for (int i = bs1.length; i < bs2.length; i++) {
263-
if (bs1[i] != 0) {
263+
if (bs2[i] != 0) {
264264
return false;
265265
}
266266
}
267267
for (int i = bs2.length; i < bs1.length; i++) {
268-
if (bs2[i] != 0) {
268+
if (bs1[i] != 0) {
269269
return false;
270270
}
271271
}

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