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Add Verilog tests
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‎opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogSymbolTokenizerTest.java

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/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* See LICENSE.txt included in this distribution for the specific
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* language governing permissions and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at LICENSE.txt.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (c) 2010, 2018, Oracle and/or its affiliates. All rights reserved.
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* Portions Copyright (c) 2017, 2019, Chris Fraire <[email protected]>.
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*/
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package org.opengrok.indexer.analysis.verilog;
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import java.io.BufferedReader;
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import java.io.InputStream;
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import java.io.InputStreamReader;
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import java.nio.charset.StandardCharsets;
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import java.util.ArrayList;
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import java.util.List;
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import org.junit.Test;
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import static org.junit.Assert.assertNotNull;
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import static org.opengrok.indexer.util.CustomAssertions.assertSymbolStream;
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/**
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* Tests the {@link VerilogSymbolTokenizer} class.
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*/
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public class VerilogSymbolTokenizerTest {
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/**
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* Test sample.v v. samplesymbols.txt
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* @throws Exception thrown on error
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*/
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@Test
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public void testVerilogSymbolStream() throws Exception {
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InputStream vRes = getClass().getClassLoader().getResourceAsStream(
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"analysis/verilog/sample.v");
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assertNotNull("despite sample.v as resource,", vRes);
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InputStream symRes = getClass().getClassLoader().getResourceAsStream(
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"analysis/verilog/samplesymbols.txt");
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assertNotNull("despite samplesymbols.txt as resource,", symRes);
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List<String> expectedSymbols = new ArrayList<>();
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try (BufferedReader symRead = new BufferedReader(new InputStreamReader(
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symRes, StandardCharsets.UTF_8))) {
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String line;
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while ((line = symRead.readLine()) != null) {
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int hashOffset = line.indexOf('#');
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if (hashOffset != -1) {
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line = line.substring(0, hashOffset);
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}
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expectedSymbols.add(line.trim());
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}
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}
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assertSymbolStream(VerilogSymbolTokenizer.class, vRes, expectedSymbols);
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}
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}

‎opengrok-indexer/src/test/java/org/opengrok/indexer/analysis/verilog/VerilogXrefTest.java

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/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* See LICENSE.txt included in this distribution for the specific
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* language governing permissions and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at LICENSE.txt.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (c) 2012, 2018, Oracle and/or its affiliates. All rights reserved.
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* Portions Copyright (c) 2017, 2019, Chris Fraire <[email protected]>.
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*/
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package org.opengrok.indexer.analysis.verilog;
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import org.junit.Test;
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import org.opengrok.indexer.analysis.AbstractAnalyzer;
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import org.opengrok.indexer.analysis.CtagsReader;
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import org.opengrok.indexer.analysis.Definitions;
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import org.opengrok.indexer.analysis.WriteXrefArgs;
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import org.opengrok.indexer.analysis.Xrefer;
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import java.io.BufferedReader;
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import java.io.ByteArrayOutputStream;
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import java.io.IOException;
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import java.io.InputStream;
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import java.io.InputStreamReader;
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import java.io.PrintStream;
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import java.io.StringWriter;
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import java.io.Writer;
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import java.nio.charset.StandardCharsets;
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import static org.junit.Assert.assertEquals;
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import static org.junit.Assert.assertNotNull;
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import static org.opengrok.indexer.util.CustomAssertions.assertLinesEqual;
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import static org.opengrok.indexer.util.StreamUtils.copyStream;
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/**
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* Tests the {@link VerilogXref} class.
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*/
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public class VerilogXrefTest {
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@Test
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public void sampleTest() throws IOException {
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writeAndCompare("analysis/verilog/sample.v",
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"analysis/verilog/sample_xref.html",
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getTagsDefinitions(), 81);
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}
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@Test
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public void shouldCloseTruncatedStringSpan() throws IOException {
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writeAndCompare("analysis/verilog/truncated.v",
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"analysis/verilog/truncated_xref.html",
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null, 1);
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}
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private void writeAndCompare(String sourceResource, String resultResource,
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Definitions defs, int expLOC) throws IOException {
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ByteArrayOutputStream bytesOut = new ByteArrayOutputStream();
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InputStream sourceRes = getClass().getClassLoader().getResourceAsStream(
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sourceResource);
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assertNotNull(sourceResource + " should get-as-stream", sourceRes);
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int actLOC = writeVerilogXref(new PrintStream(bytesOut), sourceRes, defs);
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sourceRes.close();
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InputStream resRes = getClass().getClassLoader().getResourceAsStream(
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resultResource);
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assertNotNull(resultResource + " should get-as-stream", resRes);
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byte[] expectedBytes = copyStream(resRes);
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resRes.close();
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bytesOut.close();
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String outStr = new String(bytesOut.toByteArray(), StandardCharsets.UTF_8);
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String[] gotten = outStr.split("\n");
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String expStr = new String(expectedBytes, StandardCharsets.UTF_8);
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String[] expected = expStr.split("\n");
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assertLinesEqual("Verilog xref", expected, gotten);
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assertEquals("Verilog LOC", expLOC, actLOC);
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}
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private int writeVerilogXref(PrintStream oss, InputStream iss,
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Definitions defs) throws IOException {
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oss.print(getHtmlBegin());
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Writer sw = new StringWriter();
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VerilogAnalyzerFactory fac = new VerilogAnalyzerFactory();
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AbstractAnalyzer analyzer = fac.getAnalyzer();
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analyzer.setScopesEnabled(true);
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analyzer.setFoldingEnabled(true);
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WriteXrefArgs writeArgs = new WriteXrefArgs(
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new InputStreamReader(iss, StandardCharsets.UTF_8), sw);
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writeArgs.setDefs(defs);
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Xrefer xref = analyzer.writeXref(writeArgs);
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oss.print(sw.toString());
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oss.print(getHtmlEnd());
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return xref.getLOC();
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}
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private Definitions getTagsDefinitions() throws IOException {
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InputStream res = getClass().getClassLoader().getResourceAsStream(
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"analysis/verilog/sampletags");
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assertNotNull("though sampletags should stream,", res);
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BufferedReader in = new BufferedReader(new InputStreamReader(
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res, StandardCharsets.UTF_8));
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CtagsReader rdr = new CtagsReader();
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String line;
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while ((line = in.readLine()) != null) {
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rdr.readLine(line);
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}
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return rdr.getDefinitions();
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}
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private static String getHtmlBegin() {
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return "<!DOCTYPE html>\n" +
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"<html lang=\"en\">\n" +
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"<head>\n" +
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"<meta charset=\"UTF-8\">\n" +
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"<title>sampleFile - OpenGrok cross reference" +
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" for /sampleFile</title></head><body>\n";
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}
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private static String getHtmlEnd() {
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return "</body>\n" +
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"</html>\n";
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}
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}

‎opengrok-indexer/src/test/resources/analysis/verilog/sample.v

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/*
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* MIT License
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*
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* Copyright (c) 2018 SCARV Project - <[email protected]>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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//
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// SCARV Project
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//
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// University of Bristol
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//
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// RISC-V Cryptographic Instruction Set Extension
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//
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// Reference Implementation
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//
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//
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localparam \SCARV_COP_INSN_SUCCESS = 3'b000;
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localparam SCARV_COP_INSN_ABORT = 3'b001;
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localparam SCARV_COP_INSN_BAD_INS = 3'b010;
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localparam SCARV_COP_INSN_BAD_LAD = 3'b100;
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localparam SCARV_COP_INSN_BAD_SAD = 3'b101;
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localparam SCARV_COP_INSN_LD_ERR = 3'b110;
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localparam SCARV_COP_INSN_ST_ERR = 3'b111;
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localparam \module = 3'b111;
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localparam SCARV_COP_ICLASS_PACKED_ARITH = 4'b0001;
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localparam SCARV_COP_ICLASS_TWIDDLE = 4'b0010;
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localparam SCARV_COP_ICLASS_LOADSTORE = 4'b0011;
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localparam SCARV_COP_ICLASS_RANDOM = 4'b0100;
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localparam SCARV_COP_ICLASS_MOVE = 4'b0101;
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localparam SCARV_COP_ICLASS_MP = 4'b0110;
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localparam SCARV_COP_ICLASS_BITWISE = 4'b0111;
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localparam SCARV_COP_ICLASS_AES = 4'b1000;
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localparam SCARV_COP_ICLASS_SHA3 = 4'b1001;
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localparam SCARV_COP_SCLASS_SHA3_XY = 5'b11000;
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localparam SCARV_COP_SCLASS_SHA3_X1 = 5'b11001;
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localparam SCARV_COP_SCLASS_SHA3_X2 = 5'b11010;
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localparam SCARV_COP_SCLASS_SHA3_X4 = 5'b11100;
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localparam SCARV_COP_SCLASS_SHA3_YX = 5'b11011;
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localparam SCARV_COP_SCLASS_SCATTER_B = 5'd0 ;
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localparam SCARV_COP_SCLASS_GATHER_B = 5'd1 ;
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localparam SCARV_COP_SCLASS_SCATTER_H = 5'd2 ;
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localparam SCARV_COP_SCLASS_GATHER_H = 5'd3 ;
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localparam SCARV_COP_SCLASS_ST_W = 5'd4 ;
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localparam SCARV_COP_SCLASS_LD_W = 5'd5 ;
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localparam SCARV_COP_SCLASS_ST_H = 5'd6 ;
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localparam SCARV_COP_SCLASS_LH_CR = 5'd7 ;
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localparam SCARV_COP_SCLASS_ST_B = 5'd8 ;
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localparam SCARV_COP_SCLASS_LB_CR = 5'd9 ;
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`ifdef FORMAL
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`include "fml_common.vh"
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`endif
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//
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// module: scarv_cop_cprs
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//
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// The general purpose register file used by the COP.
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//
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module scarv_cop_cprs (
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input wire g_clk , // Global clock
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output wire g_clk_req , // Clock request
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input wire g_resetn , // Synchronous active low reset.
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`ifdef FORMAL
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`VTX_REGISTER_PORTS_OUT(cprs_snoop)
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`endif
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input wire crs1_ren , // Port 1 read enable
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input wire [ 3:0] crs1_addr , // Port 1 address
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output wire [31:0] crs1_rdata , // Port 1 read data
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input wire crs2_ren , // Port 2 read enable
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input wire [ 3:0] crs2_addr , // Port 2 address
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output wire [31:0] crs2_rdata , // Port 2 read data
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input wire crs3_ren , // Port 3 read enable
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input wire [ 3:0] crs3_addr , // Port 3 address
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output wire [31:0] crs3_rdata , // Port 3 read data
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input wire [ 3:0] crd_wen , // Port 4 write enable
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input wire [ 3:0] crd_addr , // Port 4 address
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input wire [31:0] crd_wdata // Port 4 write data
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);
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// Only need a clock when doing a write.
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assign g_clk_req = crd_wen;
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// Storage for the registers
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reg [31:0] cprs [15:0];
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`ifdef FORMAL
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`VTX_REGISTER_PORTS_ASSIGNR(cprs_snoop,cprs)
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`endif
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//
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// Read port logic
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//
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assign crs1_rdata = {32{crs1_ren}} & cprs[crs1_addr];
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assign crs2_rdata = {32{crs2_ren}} & cprs[crs2_addr];
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assign crs3_rdata = {32{crs3_ren}} & cprs[crs3_addr];
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//
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// Generate logic for each register.
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//
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genvar i;
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generate for (i = 0; i < 16; i = i + 1) begin : gen_cprs
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always @(posedge g_clk) begin
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if(!g_resetn) begin
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`ifdef FORMAL
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// If running the yosys formal flow, allow initial
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// register values to be any constant value.
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#1 cprs[i] <= $anyconst;
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`else
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#1step cprs[i] <= 32'b0;
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`endif
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end else if((|crd_wen) && (crd_addr == i)) begin
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if(crd_wen[3]) cprs[i][31:24] <= crd_wdata[31:24];
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if(crd_wen[2]) cprs[i][23:16] <= crd_wdata[23:16];
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if(crd_wen[1]) cprs[i][15: 8] <= crd_wdata[15: 8];
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if(crd_wen[0]) cprs[i][ 7: 0] <= crd_wdata[ 7: 0];
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end
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end
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end endgenerate
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endmodule

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