DMA chaining

[k057]

Hi all,

For a school project I am using the RP2040 PIO to sample and hold a signal (with externals sample and hold circuits) and then do a ADC convertion using the onboard RP2040's ADC. The iteration, sample and hold + ADC convertion should happens with at a frequency of about 200kHz.

For learning purposes, I would like to implement this using DMA rather than using interupts.

The flow of a single iteration can be summarized in this loosly made flow-chart here below :)

Using this code from J. Bentham, I managed to create the first part of what I want to do (I rely on rp_devices.py).

import array, uctypes, time
from machine import mem32, Pin
from uctypes import BF_POS, BF_LEN, BFUINT32, UINT32,struct
import rp_devices as devs

PIO0_BASE = const(0x50200000)
FDEBUG = {
    "RXSTALL" : 0<<BF_POS | 4<<BF_LEN | BFUINT32,
    "RXUNDER" : 8<<BF_POS | 4<<BF_LEN | BFUINT32,
    }

FLEVEL = {
    "TX0": 0<<BF_POS | 4<<BF_LEN | BFUINT32,
    "RX0": 4<<BF_POS | 4<<BF_LEN | BFUINT32,
    }

pio0 = struct(PIO0_BASE + 0x008, FDEBUG)
RXF0 = PIO0_BASE + 0x020
def clear_PIO0_FIFO():
    print("Lets clear the PIO0 FIFO...")
    while not pio0.RXUNDER:
        mem32[RXF0]
        print("emptying RXF0")
    pio0.RXUNDER = 1
    print("Cleared, Pio0 Fdebug RXUNDER: ", pio0.RXUNDER,"\n")

clear_PIO0_FIFO() # Empty the FIFO of the PIO.  
    

This first part is to clear any remaining items in the PIO0 RX FIFO

Then I setup the ADC channel with:

# Setup ADC channel
ADC_CHAN = 0
ADC_PIN  = 26 + ADC_CHAN
adc = devs.ADC_DEVICE
pin = devs.GPIO_PINS[ADC_PIN]
pad = devs.PAD_PINS[ADC_PIN]
pin.GPIO_CTRL_REG = devs.GPIO_FUNC_NULL
pad.PAD_REG = 0
adc.CS_REG = adc.FCS_REG = 0 # Reset the ADC CTRL register.
adc.CS.EN = 1                # Enable ADC.
adc.CS.AINSEL = ADC_CHAN     # Analog input MUX
adc.CS.RROBIN = 0            # Round-robin sampling
adc.FCS.EN = adc.FCS.DREQ_EN = 1 # Enable ADC DREQ
adc.DIV_REG = 0 << 8 # Max speed
adc.FCS.THRESH = 1 # Threshold of DREQ,
while adc.FCS.LEVEL:
    adc.FIFO_REG                  # Clear the ADC FIFO.
adc.FCS.OVER = adc.FCS.UNDER = 1  # Clear any OVER or UNDER flag for the FIFO after emptying.

Then I initialize the DMAs.
DMA0 is triggered by DREQ_PIO0_RX0 (when I call push() in the PIO program), and trigger the START_ONCE bit of the ADC.
Once the ADC finished with its single convertion, it will trigger DMA2.
DMA2 is triggered by DREQ_ADC, and move the results of the convertion from the ADC FIFO to a buffer array, adc_buf.

# Initialize DMAs
DMA_CHAN0 = const(0)
DMA_CHAN1 = const(1)
DMA_CHAN2 = const(2)
dma_chan0 = devs.DMA_CHANS[DMA_CHAN0]  # DMA trigger ADC START_ONCE
dma_chan1 = devs.DMA_CHANS[DMA_CHAN1]  # DMA retrigger DMA0
dma_chan2 = devs.DMA_CHANS[DMA_CHAN2]  # DMA transfer ADC results

dma = devs.DMA_DEVICE

# Setup DMA0 trigger ADC START_ONCE
arr_START_ONCE = array.array("I",[(mem32[devs.ADC_BASE] | 1<<2)])
dma_chan0.READ_ADDR_REG = uctypes.addressof(arr_START_ONCE) # Set ADC CTRL register 2th bit high = CS start once.
dma_chan0.WRITE_ADDR_REG = devs.ADC_BASE # Write to ADC_BASE.
dma_chan0.TRANS_COUNT_REG = 1            # Number of write.
dma_chan0.CTRL_TRIG_REG = 0              # Reset CTRL TRIG register
dma_chan0.CTRL_TRIG.CHAIN_TO = DMA_CHAN0 # chain to itself
dma_chan0.CTRL_TRIG.INCR_READ = dma_chan0.CTRL_TRIG.INCR_WRITE = 0 # No write nor read increment
dma_chan0.CTRL_TRIG.DATA_SIZE = 0x02
dma_chan0.CTRL_TRIG.IRQ_QUIET = 1
dma_chan0.CTRL_TRIG.TREQ_SEL = 4 # DREQ_PIO0_RX0
dma_chan0.CTRL_TRIG.EN = 0


# Setup DMA1, read ADC FIFO.
adc_buf = array.array("I",[0,0,0]) # ADC buffer
dma_chan1.READ_ADDR_REG = devs.ADC_FIFO_ADDR # FIFO ADDR
dma_chan1.WRITE_ADDR_REG = uctypes.addressof(adc_buf)
dma_chan1.TRANS_COUNT_REG = 1            # Number of sample
dma_chan1.CTRL_TRIG_REG = 0              # Reset CTRL TRIG register
dma_chan1.CTRL_TRIG.CHAIN_TO = DMA_CHAN1 # Chain to itself, no-chain
dma_chan1.CTRL_TRIG.INCR_WRITE = 1
dma_chan1.CTRL_TRIG.IRQ_QUIET = 1
dma_chan1.CTRL_TRIG.TREQ_SEL = devs.DREQ_ADC # DREQ_ADC
dma_chan1.CTRL_TRIG.DATA_SIZE = 1
dma_chan1.CTRL_TRIG.EN = 0

print("After DMA setup, before PIO, ADC FIFO contains: ",adc.FCS.LEVEL, " items")
print("After DMA setup, before PIO, ADC buffer contains: ",adc_buf)

Now I define my PIO program, that will blink the onboard LED, do apush(), do a DREQ_PIO0_RX0, trigger the DMA0, which trigger ADC START_ONCE, which will do a ADC_DREQ, that will activate the DMA2 to move the ADC results to the buffer array.

@rp2.asm_pio(set_init=(rp2.PIO.OUT_LOW,)*1)
def fun():
    set(pins,1) [30]
    push() # DREQ 4, DREQ_PIO0_RX0
    set(pins,0)
    #push() 
    wait(1,pins,0)
    
measure_sm = rp2.StateMachine(0, fun,
                              freq=5_000,
                              set_base=Pin(25),in_base=Pin(1))

dma_chan0.CTRL_TRIG.EN = 1
dma_chan1.CTRL_TRIG.EN = 1

measure_sm.active(1)
time.sleep(0.01)
measure_sm.active(0)

print("After PIO, ADC FIFO contains: ",adc.FCS.LEVEL, " items")
print("After PIO, ADC buffer contains: ",adc_buf)

Well so far so good, this is the output on the REPL:

Lets clear the PIO0 FIFO...
emptying RXF0
emptying RXF0
Cleared, Pio0 Fdebug RXUNDER:  0 

After DMA setup, before PIO, ADC FIFO contains:  0  items
After DMA setup, before PIO, ADC buffer contains:  array('I', [0, 0, 0])
After PIO, ADC FIFO contains:  0  items
After PIO, ADC buffer contains:  array('I', [83, 0, 0])

And the ADC buffer contains the value of the conversion as it should. (I attach this full code here for easy copy-paste 11_3_PIO_ADC_BUFFER_Q.zip)

Now my objective is to get my two DMAs retriggered in the same order if I call a second time the push() function. By getting inspired by Van Hunter Adams'code, I though that all my problems could be solved by chaining a third DMA (channel2) to DMA1 which would re-trigger DMA0.

There its were I am getting a bit confused.
For debug purpose, rather than trying to retrigger DMA0, I decided to code the DMA2 to have it chained to DMA0 and only move some values between two arrays (ar1, ar2) so I could eye-ball the behaviour. The full code is downloadable here: 11_4_PIO_ADC_BUFFER_DMA2_Q.zip.
and reported here below:

import array, uctypes, time
from machine import mem32, Pin
from uctypes import BF_POS, BF_LEN, BFUINT32, UINT32,struct
import rp_devices as devs
PIO0_BASE = const(0x50200000)
FDEBUG = {
    "RXSTALL" : 0<<BF_POS | 4<<BF_LEN | BFUINT32,
    "RXUNDER" : 8<<BF_POS | 4<<BF_LEN | BFUINT32,
    }
FLEVEL = {
    "TX0": 0<<BF_POS | 4<<BF_LEN | BFUINT32,
    "RX0": 4<<BF_POS | 4<<BF_LEN | BFUINT32,
    }
pio0 = struct(PIO0_BASE + 0x008, FDEBUG)
RXF0 = PIO0_BASE + 0x020
def clear_PIO0_FIFO():
    print("Lets clear the PIO0 FIFO...")
    while not pio0.RXUNDER:
        mem32[RXF0]
        print("emptying RXF0")
    pio0.RXUNDER = 1
    print("Cleared, Pio0 Fdebug RXUNDER: ", pio0.RXUNDER,"\n")
clear_PIO0_FIFO() # Empty the FIFO of the PIO.  
# Setup ADC channel
ADC_CHAN = 0
ADC_PIN  = 26 + ADC_CHAN
adc = devs.ADC_DEVICE
pin = devs.GPIO_PINS[ADC_PIN]
pad = devs.PAD_PINS[ADC_PIN]
pin.GPIO_CTRL_REG = devs.GPIO_FUNC_NULL
pad.PAD_REG = 0
adc.CS_REG = adc.FCS_REG = 0 # Reset the ADC CTRL register.
adc.CS.EN = 1                # Enable ADC.
adc.CS.AINSEL = ADC_CHAN     # Analog input MUX
adc.CS.RROBIN = 0            # Round-robin sampling
adc.FCS.EN = adc.FCS.DREQ_EN = 1 # Enable ADC DREQ
adc.DIV_REG = 0 << 8 # Max speed
adc.FCS.THRESH = 1 # Threshold of DREQ,
while adc.FCS.LEVEL:
    adc.FIFO_REG                  # Clear the ADC FIFO.
adc.FCS.OVER = adc.FCS.UNDER = 1  # Clear any OVER or UNDER flag for the FIFO after emptying.
# Initialize DMAs
DMA_CHAN0 = const(0)
DMA_CHAN1 = const(1)
DMA_CHAN2 = const(2)
dma_chan0 = devs.DMA_CHANS[DMA_CHAN0]  # DMA trigger ADC START_ONCE
dma_chan1 = devs.DMA_CHANS[DMA_CHAN1]  # DMA retrigger DMA0
dma_chan2 = devs.DMA_CHANS[DMA_CHAN2]  # DMA transfer ADC results
dma = devs.DMA_DEVICE
# Setup DMA0 trigger ADC START_ONCE
arr_START_ONCE = array.array("I",[(mem32[devs.ADC_BASE] | 1<<2)])
dma_chan0.READ_ADDR_REG = uctypes.addressof(arr_START_ONCE) # Set ADC CTRL register 2th bit high = CS start once.
dma_chan0.WRITE_ADDR_REG = devs.ADC_BASE # Write to ADC_BASE.
dma_chan0.TRANS_COUNT_REG = 1            # Number of write.
dma_chan0.CTRL_TRIG_REG = 0              # Reset CTRL TRIG register
dma_chan0.CTRL_TRIG.CHAIN_TO = DMA_CHAN2 # chain channel 2
dma_chan0.CTRL_TRIG.INCR_READ = dma_chan0.CTRL_TRIG.INCR_WRITE = 0 # No write nor read increment
dma_chan0.CTRL_TRIG.DATA_SIZE = 0x02
dma_chan0.CTRL_TRIG.IRQ_QUIET = 1
dma_chan0.CTRL_TRIG.TREQ_SEL = 4 # DREQ_PIO0_RX0
dma_chan0.CTRL_TRIG.EN = 0
# Setup DMA1, read ADC FIFO.
adc_buf = array.array("I",[0,0,0]) # ADC buffer
dma_chan1.READ_ADDR_REG = devs.ADC_FIFO_ADDR # FIFO ADDR
dma_chan1.WRITE_ADDR_REG = uctypes.addressof(adc_buf)
dma_chan1.TRANS_COUNT_REG = 1            # Number of sample
dma_chan1.CTRL_TRIG_REG = 0              # Reset CTRL TRIG register
dma_chan1.CTRL_TRIG.CHAIN_TO = DMA_CHAN1 # Chain to itself, no-chain
dma_chan1.CTRL_TRIG.INCR_WRITE = 1
dma_chan1.CTRL_TRIG.IRQ_QUIET = 1
dma_chan1.CTRL_TRIG.TREQ_SEL = devs.DREQ_ADC # DREQ_ADC
dma_chan1.CTRL_TRIG.DATA_SIZE = 1
dma_chan1.CTRL_TRIG.EN = 0

# Setup DMA2, move two values between ar1, ar2
ar1 = array.array("I",[1]) 
ar2 = array.array("I",[0]) 
dma_chan2.READ_ADDR_REG = uctypes.addressof(ar1) # FIFO ADDR
dma_chan2.WRITE_ADDR_REG = uctypes.addressof(ar2)
dma_chan2.TRANS_COUNT_REG = 1            # Number of sample
dma_chan2.CTRL_TRIG_REG = 0              # Reset CTRL TRIG register
dma_chan2.CTRL_TRIG.CHAIN_TO = DMA_CHAN2 # Chain to itself, no-chain
dma_chan2.CTRL_TRIG.INCR_WRITE = 1
dma_chan2.CTRL_TRIG.IRQ_QUIET = 1
dma_chan2.CTRL_TRIG.TREQ_SEL = 0x3f # unpaced
dma_chan2.CTRL_TRIG.DATA_SIZE = 0x02
dma_chan2.CTRL_TRIG.EN = 0

print("After DMA setup, before PIO, ADC buffer contains: ",adc_buf)
print("After DMA setup, ar1, ar2 contains: ",ar1,ar2)
@rp2.asm_pio(set_init=(rp2.PIO.OUT_LOW,)*1)
def fun():
    set(pins,1) [30]
    #push() # DREQ 4, DREQ_PIO0_RX0
    set(pins,0)
    #push() 
    wait(1,pins,0)  
measure_sm = rp2.StateMachine(0, fun,
                              freq=5_000,
                              set_base=Pin(25),in_base=Pin(1))
dma_chan0.CTRL_TRIG.EN = 1
dma_chan1.CTRL_TRIG.EN = 1
dma_chan2.CTRL_TRIG.EN = 1
measure_sm.active(1)
time.sleep(0.01)
measure_sm.active(0)
print("After PIO, ADC buffer contains: ",adc_buf)
print("After PIO, ar1, ar2 contains: ",ar1,ar2)

What I don't understand is that if I call the push() function or I comment it out, the DMA0 will or will not take place. On the other hand, the DMA2 will always transfer the value from ar1 to ar2 even if DMA0 was not triggered
Why is this behaviour happening? Even if it is an unpaced transfer, shouldn't it be chained to DMA0 and happens only when DMA0 takes place? Where could I be wrong?

It is quite of a long post, I hope I managed to convey the problem in a clear way :)

Best,
Martino

[rkompass]

Mhm, that looks complicated.
To summarize what I understood:
(a) The PIO program flashes the LED once and then waits for Pin 1 to go high. It pushes a value to the output FIFO.
This sets a data request, which is evaluated by DMA0.

DMA0 is triggered by DREQ_PIO0_RX0 (when I call push() in the PIO program), and trigger the START_ONCE bit of the ADC.

(b) DMA0 is programmed to be timed by this DREQ. It transfers one word to the ADC config register that sets CS.START_ONCE

Writing a 1 to CS.START_ONCE will immediately start a new conversion. CS.READY will go low, to show that a
conversion is currently in progress. After 96 cycles of clk_adc, CS.READY will go high. The 12-bit conversion result is
available in RESULT. (from the Datasheet)

This of course has to happen from a storage location that is fixed, no read increment. The same respective value is written to this ADC register again and again, eliciting the ADC conversion every time. ADC has to be set for One-shot Sample.

(c) Another DMA channel (you referred to DMA2, but it might be counted as DMA1) evaluates the DREQ of the ADC and stores the result of the conversion. This may happen in a cyclic manner so that a sufficiently large buffer is written again and again and one only has to poll the DMA writing address in that buffer to extract the values before they get overwritten in the next cycle.

If you want all this to happen in an automatic manner, with 200kHz you have to make sure that the PIO, which has its own timer, is running at that frequency. I do not see the need for a third DMA.

The parts (a) (b) and (c) may be tested independently. For (c) the ADC may be set to Free-running Sampling. The DMA then should be able to store the values.

What I don't understand is that if I call the push() function or I comment it out, the DMA0 will or will not take place. On the other hand, the DMA2 will always transfer the value from ar1 to ar2 even if DMA0 was not triggered
Why is this behaviour happening? Even if it is an unpaced transfer, shouldn't it be chained to DMA0 and happens only when DMA0 takes place? Where could I be wrong?

It seems you do the transfer from ar1 to ar2 for testing, right? So you can check whether the DMA2 transfer happened?
In the end DMA2 should transfer from the ADC FIFO to another, larger array.
Perhaps the ADC is not set to One-shot Sample, then the DMA2 transfer would be triggered at the sampling rate of the ADC Free-running Sampling.

[k057]

Hi, thanks for your answer and yes I might have exposed the problem maybe in a too convulated way.
The part a) , b) and c) are indeed what you described and they work well, the problem is that at the moment this loop is done only once.
I am trying to figure out a way to "re-load" the transfer count of DMA0 and re-trigger it, so that at the next push() call it will do the same iteration.
I am trying to write in upython this example of the C SDK, probably it will give me a better understanding of what I need to do. I have the feel that the DMA aliases are the way to go...

[rkompass]

@k057
I had a look at your code for DMA0 and found one probable culprit:
dma_chan0.TRANS_COUNT_REG = 1 # Number of write.
You might want to set this to a higher value, i.e. as many transfers/ADC readings as you want to do in total.
The thing is, as the DMA transfer is paced by TREQ_SEL anyway, each time you have a push() by the PIO it will only transfer once, the transfer count decreases by one.
You can test this by reading the dma_chan0.TRANS_COUNT_REG.

[k057]

@rkompass
Yes I had that on purpose.
I agree that if I increase it, I can make more transfers.

On the other hand, if I want to use DMA to time-critically triggers the ADC to convert the sampled-and-hold signal at the correct moment, and repeat this operation over time (at high frequency for minutes, hours) I would need to set a transfer counts of thousands (millions) of times.

Is it possible to define a DMA channel that is triggered by a DREQ and at the end of its sequence is resetted and ready to trigger at the next DREQ?
Is it possible to reload a channel counter WITHOUT triggering the channel (and let it wait for a DREQ)?

I thought that the way to go was to make all the transfers once, and then re-load the transfer counts of the whole series of DMAs.
But then there will still be a problem because I will still need to set a transfer count of the "re-loading DMA" as high as the number of transfer that I want to do.

When I see some example in where DMA do "ping-pong" I have the feel that it is possible to have a DMA that loops over itself until it is disabled.

EDIT: do you know what happens to the transfer count when the channel is re-triggered (lets say by chaining)?

EDIT2: got my answer from the datasheet:

Each time the channel starts a new transfer sequence, the most recent value written to TRANS_COUNT is copied to the live
transfer counter, which will then start to decrement again as the new transfer sequence makes progress. For debugging
purposes, the last value written can be read from the DBG_TCR (TRANS_COUNT reload value) register

[rkompass]

@k057

Is it possible to reload a channel counter WITHOUT triggering the channel (and let it wait for a DREQ)?

Yes. On page 94 of the datasheet (in section 2.5.2.1) you have 3 aliases i.e. addresses for the transfer count register that do not trigger.

On the other hand, if I want to use DMA to time-critically triggers the ADC to convert the sampled-and-hold signal at the correct moment, and repeat this operation over time (at high frequency for minutes, hours) I would need to set a transfer counts of thousands (millions) of times.

Yes, but that's not a problem if you use the ring RING_SEL and RING_SIZE options of the control register. For DMA0 you still only need a buffer of size 1. But the transfer (of the ADCed values) will then be cyclically write to the same buffer. The buffer may be up to 32768 in size. This happens by just modifying only n lower bits of the address register counter. Important: You buffer has to be aligned to that address size, otherwise it will write to positions before the start of the buffer while counting cyclically this way. This is a bit tricky as MP has no standard option to achieve that.

You can then read the position of the address or transfer register in time intervals (use cyclic schedule perhaps for that) to check whether to evaluate new data.

That's the way I would try to do it, but of course you may set up ping pong or another way of re-triggering with another DMA1, especially for learning purpose :-). Just try to avoid to solve many new problems simultaneously, as you might not understand where simultaneous issues arise from.

[k057]

Thanks @rkompass
I have the feeling that I am drowning in a glass of water, that motivate me to find the solution. I simplified my first code for easier debug. I have now only one DMA channel that is triggered by DREQ_PIO0_RX0 (push()). This DMA channel moves a value from array a to an array b. Code at the end of the post. Here were to get the rp_devices.zip file.

Yes. On page 94 of the datasheet (in section 2.5.2.1) you have 3 aliases i.e. addresses for the transfer count register that do not trigger.

Indeed, if I write to the CH0_AL2_TRANS_COUNT (offset: 0x024) I change the TRANS_COUNT register without triggering the DMA, but I change the TRANS_COUNT for the next transfer.
P.112

Writing this register sets the RELOAD value for the transfer counter. Each time
this channel is triggered, the RELOAD value is copied into the live transfer
counter.

EDIT2: I also read that:

Trigger registers do not start the channel if:
•The channel is disabled via CTRL.EN. (If the trigger is CTRL, the just-written value of EN is used, not the value currently in the CTRL register.)

So now my code activate the DMA, the DMA is triggered by the DREQ of the PIO0, do the transfer and then idle. If I write to the TRANS_COUNT register of one of the aliases it is still waiting for the next trigger (but the DREQ doesn't trigger anymore a new transfer).

Yes, but that's not a problem if you use the ring RING_SEL and RING_SIZE options of the control register. For DMA0 you still only need a buffer of size 1. But the transfer (of the ADCed values) will then be cyclically write to the same buffer.

True, I found some post indicating this.

import array, uctypes, time
from machine import mem32, Pin
from uctypes import BF_POS, BF_LEN, BFUINT32, UINT32,struct
import rp_devices as devs

PIO0_BASE = const(0x50200000)
RXF0 = PIO0_BASE + 0x020
FDEBUG = {
    "RXSTALL" : 0<<BF_POS | 4<<BF_LEN | BFUINT32,
    "RXUNDER" : 8<<BF_POS | 4<<BF_LEN | BFUINT32,
    }
pio0 = struct(PIO0_BASE + 0x008, FDEBUG)
def clear_PIO0_FIFO():
    while not pio0.RXUNDER:
        mem32[RXF0]
    pio0.RXUNDER = 1
clear_PIO0_FIFO() # Empty the FIFO of the PIO.  

CH0_AL2_TRANS_COUNT = const(0x024)
# Initialize DMAs
DMA_CHAN0 = const(0)
dma_chan0 = devs.DMA_CHANS[DMA_CHAN0]  #
dma = devs.DMA_DEVICE

a = array.array("I",[1])
b = array.array("I",[0,0])
dma_chan0.READ_ADDR_REG = uctypes.addressof(a) 
dma_chan0.WRITE_ADDR_REG = uctypes.addressof(b)  #
dma_chan0.TRANS_COUNT_REG = 1            # One transfer
dma_chan0.CTRL_TRIG_REG = 0              # Reset register for writing
dma_chan0.CTRL_TRIG.CHAIN_TO = DMA_CHAN0 # Chain to itself
dma_chan0.CTRL_TRIG.INCR_READ = 0        # Read same place of array
dma_chan0.CTRL_TRIG.INCR_WRITE = 1       # Write to new place in the array
dma_chan0.CTRL_TRIG.DATA_SIZE = 0x02     # 32bit word
dma_chan0.CTRL_TRIG.IRQ_QUIET = 1        # No IRQ
dma_chan0.CTRL_TRIG.TREQ_SEL = 4         # DREQ_PIO0_RX0
dma_chan0.CTRL_TRIG.HIGH_PRIORITY = 0    # No High priority
dma_chan0.CTRL_TRIG.EN = 1               # Start the channel

print("After DMA setup and EN, a and b are: ",a, b)
print("After DMA setup and EN, CH0_AL1_TRANS_COUNT is: ",mem32[devs.DMA_BASE+CH0_AL2_TRANS_COUNT])

@rp2.asm_pio(set_init=(rp2.PIO.OUT_LOW,)*1)
def fun():
    set(pins,1) [30]
    push() # DREQ 4, DREQ_PIO0_RX0
    set(pins,0)
    #push() # If I push a second time, the DMA doesn't re-start
    wait(1,pins,0)
    
measure_sm = rp2.StateMachine(0, fun,
                              freq=5_000,
                              set_base=Pin(25),in_base=Pin(1))

measure_sm.active(1)
time.sleep(0.01)
measure_sm.active(0)

print("\n")
print("After DREQ_PIO0_RX0, a and b are: ",a, b)
print("After DREQ_PIO0_RX0, CH0_AL2_TRANS_COUNT is: ",mem32[devs.DMA_BASE+CH0_AL2_TRANS_COUNT])

mem32[devs.DMA_BASE+CH0_AL2_TRANS_COUNT] = 1 # Manually increase the TRANS_COUNT
print("\n")
print("After MANUAL increase of of TRANS_COUNT,a,b array are: ",a, b)
print("After MANUAL increase of of TRANS_COUNT, the TRANS_COUNT is: ",mem32[devs.DMA_BASE+CH0_AL2_TRANS_COUNT])

EDIT: Forgot to add the output of the code:

After DMA setup and EN, a and b are:  array('I', [1]) array('I', [0, 0])
After DMA setup and EN, CH0_AL1_TRANS_COUNT is:  1

After DREQ_PIO0_RX0, a and b are:  array('I', [1]) array('I', [1, 0])
After DREQ_PIO0_RX0, CH0_AL2_TRANS_COUNT is:  0

After MANUAL increase of of TRANS_COUNT,a,b array are:  array('I', [1]) array('I', [1, 0])
After MANUAL increase of of TRANS_COUNT, the TRANS_COUNT is:  0