Cannot access all RAM in STM32 NUCLEO_H723ZG port

[saraverbeecke]

Hi,

I successfully built and flashed a NUCLEO_H723ZG board with MicroPython v1.20.
When I check the RAM after a clean hard reset:

import gc
gc.collect()
gc.mem_free()

I get: 74416 bytes

The specs of the STM32H723ZG indicate:

• 28 Kbytes of data TCM RAM for critical real time data
• 432 Kbytes of system RAM (up to 256 Kbytes can remap on instruction TCM RAM for critical real time instructions)
• 4 Kbytes of backup SRAM (available in the lowest-power modes)

Any idea why I get no value near 400 kB?
Thanks!

[robert-hh]

The loader script seems to configur for 128k+128k RAM. So maybe that one has to be changed.

[saraverbeecke]

Thanks for pointing to that file @robert-hh.

stm32h723.ld contains:

...
/* Specify the memory areas */
MEMORY
{
    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 768K    /* sectors 0-5 */
    FLASH_APP  (rx) : ORIGIN = 0x08020000, LENGTH = 640K    /* sectors 1-5 */
    FLASH_FS (r)    : ORIGIN = 0x080c0000, LENGTH = 256K    /* sectors 6-7 */
    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for FS storage cache */
    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 128K    /* AXI SRAM (could extend +192K from ITCM) */
    RAM_SRAM1 (xrw) : ORIGIN = 0x30000000, LENGTH = 16K     /* SRAM1 */
}
...

Can I just change it to the following?

...
/* Specify the memory areas */
MEMORY
{
    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 768K    /* sectors 0-5 */
    FLASH_APP  (rx) : ORIGIN = 0x08020000, LENGTH = 640K    /* sectors 1-5 */
    FLASH_FS (r)    : ORIGIN = 0x080c0000, LENGTH = 256K    /* sectors 6-7 */
    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for FS storage cache */
    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 432K    /* AXI SRAM (could extend +192K from ITCM) */
    RAM_SRAM1 (xrw) : ORIGIN = 0x30000000, LENGTH = 16K     /* SRAM1 */
}
...

[jimmo]

@saraverbeecke This needs to be configured in the flash option bytes. Although I think the default value does give you 64kiB ICTM and therefore the additional 192kiB for AXI SRAM.

See the heading "RAM shared between ITCM and AXI RAM" in the reference manual (ST RM0468).

[saraverbeecke]

@jimmo thanks for looking into this. But what do you mean by "needs to be configured in the flash option bytes".
Do you mean I add it to the DTCM (xrw) line instead of the AXI SRAM?

..
/* Specify the memory areas */
MEMORY
{
    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 768K    /* sectors 0-5 */
    FLASH_APP  (rx) : ORIGIN = 0x08020000, LENGTH = 640K    /* sectors 1-5 */
    FLASH_FS (r)    : ORIGIN = 0x080c0000, LENGTH = 256K    /* sectors 6-7 */
    DTCM (xrw)      : ORIGIN = 0x20000000, LENGTH = 432K    /* Used for FS storage cache */
    RAM (xrw)       : ORIGIN = 0x24000000, LENGTH = 128K  /* AXI SRAM (could extend +192K from ITCM) */
    RAM_SRAM1 (xrw) : ORIGIN = 0x30000000, LENGTH = 16K     /* SRAM1 */
}
...

I'm no RAM expert :-)

[jimmo]

Option bytes are persistent configuration registers. You can set them via st-link using e.g. Cube Programmer.

You'll need to refer to the reference manual I mentioned, but there's a two-bit setting (TCM_AXI_SHARED) in the option byte (FLASH_OPTSR2_PRG) that lets you configure how the memory layout works.

RM0468 details how this works, see page 133 for the memory layout.
0x24000000 - 0x2401FFFF (128kiB) is AXI SRAM. (this is what the .ld file is configured to use)
0x24020000 - 0x2404FFFF (192kiB) is an additional region that may be mapped depending on the option byte setting. Anything you don't map here will be assigned to ITCM at 0x00000000.

The minimum split for ITCM (64kiB) gives the full additional 192kiB of AXI SRAM (320kiB total), the maximum split (all 192kiB for ITCM) gives none (128kiB total). This is described on page 141.

So if TCM_AXI_SHARED is set to 0b00, then yes you can set the length of the RAM region in the .ld file to 320kiB. But if it's set to 0b11 then you must leave it as it is. Like I said the default appears to be 0b00.

[jimmo]

(The important thing to note is that 0x24000000 - 0x2401FFFF is adjacent to 0x24020000 - 0x2404FFFF, so if you've mapped the additional region, then you can just treat it as one large AXI SRAM region)

[jimmo]

What MicroPython should do here is set up both regions in the linker script separately, and then when configuring the heap it should query the option byte at runtime and figure out what it is allowed to use for the heap (using the new split heap feature that allows multiple heap regions to be defined).

[saraverbeecke]

Isn't there a way the set the option bytes without a st-link (using e.g. Cube Programmer) for now, since I don't have one...

[jimmo]

The Nucleo has one built-in?