Rising/falling information in GPIO INTR* registers cleared for GPIOs without interrupts enabled #13129
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smacx250
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RP2040 / Pico
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I was intending to use polling of the GPIO INTR* registers to determine if/how pins had transitioned during the polling interval. However, I found that "sometimes", "something", was clearing that information, making it unreliable. I found that it was due to this code in machine_pin.c:
What is happening is that the code loops over every GPIO, and if it finds status for a GPIO (which it always will, because at least one of the "level" bits will always be set), it calls "gpio_acknowledge_irq", which clears the (clearable) status in the INTR* register. This is done regardless if interrupts are enabled for the GPIO, or not.
I don't know the real intention for this, but I find myself wondering if something like the following may be "better"?
The change looks at the actual interrupt status registers, after masking for the interrupts being enabled, instead of the raw GPIO status. The effect of this is that the acknowledgment code will only be run for GPIOs which actually have a non-masked interrupt asserted, instead of every GPIO. A side effect of this is that the GPIO status bits in the INTR* registers will not be cleared for GPIOs that don't have any interrupts enabled, allowing the transition information there to be used for polling.
Any thoughts on this?
Thanks!
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