Unable to wakeup with pin from deepsleep with NUCLEO_L452RE

[Tico06]

Hi All,

I would like to experiment with deepsleep in uPy. Currently I am playing with a NUCLEO-L452RE. I had no success to wakeup from deepsleep with the help of USER_B1, while successfully did from lightsleep with the following piece of code:

>>> p = machine.Pin('USER_B1', machine.Pin.IN, machine.Pin.PULL_UP)
>>> p.irq(trigger=machine.Pin.IRQ_RISING, handler=lambda p:None)
>>> machine.lightsleep()

Searching in issues and discussions from GitHub, I found this answer from Damien:
#3834 (comment)

But to exit from machine.deepsleep() you must use X1 (=PA0) and it requires special code to enable this feature:

import stm
stm.mem32[stm.PWR + stm.PWR_CSR] |= 1 << 8 # enable WKUP pin on PA0
machine.deepsleep()

X1 will be in input pull-down mode and will wake the MCU when it goes high. Unfortunately there is no way to make it pull-up and wake when it goes low (deep sleep is very low power consumption and only a handful of features are enabled during this mode).

• Is this still relevant ?
• Any clue how to wakeup from other capable Pins like PA0, PC13, PE6, PA2, PC5
• Do we have now a more portable way (Working on different MCUs) to do this ?

Thanks and reg

Eric.

[Tico06]

Hi All,

I am stuck here. I tried to use the piece of code from Damien above, but stm.PWR_CSR doesn't exist for L452. I had a look in https://github.com/peterhinch/micropython-micropower/blob/master/upower.py, hoping WakeupPin would fit better, but same issue with stm.PWR_CSR2.

Anyone to support me in experimenting deepsleep and wakeup_pin please ?

Thanks and best regards,
Eric.

[Tico06]

Hi There,

I gave it another try with PA0, with or without pull-down resistor it doesn't wakeup. Here is my short code:

>>> p = machine.Pin('A0', machine.Pin.IN, machine.Pin.PULL_DOWN)
>>> p.irq(trigger=machine.Pin.IRQ_RISING, handler=lambda p:None)
>>> machine.deepsleep()

No chance... The board never wakes up when I trigger PA0

Please could someone give me directions to sort out this ? or maybe it's not supported ?

Thanks and regards,

Eric.

[Tico06]

Hi Guys,

Still investigating on waking up my nucleo-l452 from a pin. I found this thread:
How to enter Standby or Shutdown mode on STM32
and tried to implement in mp as following:

# https://libopencm3.org/docs/latest/stm324/html/group__cm__scb__registers.html#ga046351cf4159d1e8953730326c31ec5c
# ******************* memorymap.h
PPBI_BASE = 0xE0000000
SCS_BASE =  PPBI_BASE + 0xE000
SCB_BASE = SCS_BASE + 0x0D00
SCB_SCR = SCB_BASE + 0x10

# STM32CubeL4/Drivers/CMSIS/Include/core_cm3.h
#
# *SCB System Control Register Definitions*
SCB_SCR_SEVONPEND_Pos = 4                                            # !< SCB SCR: SEVONPEND Position
SCB_SCR_SEVONPEND_Msk = (1 << SCB_SCR_SEVONPEND_Pos)                 # !< SCB SCR: SEVONPEND Mask

SCB_SCR_SLEEPDEEP_Pos = 2                                            # !< SCB SCR: SLEEPDEEP Position
SCB_SCR_SLEEPDEEP_Msk = (1 << SCB_SCR_SLEEPDEEP_Pos)                 # !< SCB SCR: SLEEPDEEP Mask

SCB_SCR_SLEEPONEXIT_Pos = 1                                            # !< SCB SCR: SLEEPONEXIT Position
SCB_SCR_SLEEPONEXIT_Msk = (1 << SCB_SCR_SLEEPONEXIT_Pos)               # !< SCB SCR: SLEEPONEXIT Mask

# stm32ib/CMSIS/STM324xx/Include/stm32l452xx.h
#
# *******************  Bit definition for PWR_PUCRA register  ********************/
PWR_PUCRA_PA15_Pos = 15
PWR_PUCRA_PA15_Msk = (0x1 << PWR_PUCRA_PA15_Pos)             # !< 0x00008000
PWR_PUCRA_PA15 = PWR_PUCRA_PA15_Msk                        # !< Port PA15 Pull-Up set
PWR_PUCRA_PA13_Pos = 13
PWR_PUCRA_PA13_Msk = (0x1 << PWR_PUCRA_PA13_Pos)             # !< 0x00002000
PWR_PUCRA_PA13 = PWR_PUCRA_PA13_Msk                        # !< Port PA13 Pull-Up set
PWR_PUCRA_PA12_Pos = 12
PWR_PUCRA_PA12_Msk = (0x1 << PWR_PUCRA_PA12_Pos)             # !< 0x00001000
PWR_PUCRA_PA12 = PWR_PUCRA_PA12_Msk                        # !< Port PA12 Pull-Up set
PWR_PUCRA_PA11_Pos = 11
PWR_PUCRA_PA11_Msk = (0x1 << PWR_PUCRA_PA11_Pos)             # !< 0x00000800
PWR_PUCRA_PA11 = PWR_PUCRA_PA11_Msk                        # !< Port PA11 Pull-Up set
PWR_PUCRA_PA10_Pos = 10
PWR_PUCRA_PA10_Msk = (0x1 << PWR_PUCRA_PA10_Pos)             # !< 0x00000400
PWR_PUCRA_PA10 = PWR_PUCRA_PA10_Msk                        # !< Port PA10 Pull-Up set
PWR_PUCRA_PA9_Pos = 9
PWR_PUCRA_PA9_Msk = (0x1 << PWR_PUCRA_PA9_Pos)              # !< 0x00000200
PWR_PUCRA_PA9  = PWR_PUCRA_PA9_Msk                         # !< Port PA9 Pull-Up set 
PWR_PUCRA_PA8_Pos = 8
PWR_PUCRA_PA8_Msk = (0x1 << PWR_PUCRA_PA8_Pos)              # !< 0x00000100
PWR_PUCRA_PA8  = PWR_PUCRA_PA8_Msk                         # !< Port PA8 Pull-Up set 
PWR_PUCRA_PA7_Pos = 7
PWR_PUCRA_PA7_Msk = (0x1 << PWR_PUCRA_PA7_Pos)              # !< 0x00000080
PWR_PUCRA_PA7  = PWR_PUCRA_PA7_Msk                         # !< Port PA7 Pull-Up set 
PWR_PUCRA_PA6_Pos = 6
PWR_PUCRA_PA6_Msk = (0x1 << PWR_PUCRA_PA6_Pos)              # !< 0x00000040
PWR_PUCRA_PA6  = PWR_PUCRA_PA6_Msk                         # !< Port PA6 Pull-Up set 
PWR_PUCRA_PA5_Pos = 5
PWR_PUCRA_PA5_Msk = (0x1 << PWR_PUCRA_PA5_Pos)              # !< 0x00000020
PWR_PUCRA_PA5  = PWR_PUCRA_PA5_Msk                         # !< Port PA5 Pull-Up set 
PWR_PUCRA_PA4_Pos = 4
PWR_PUCRA_PA4_Msk = (0x1 << PWR_PUCRA_PA4_Pos)              # !< 0x00000010
PWR_PUCRA_PA4  = PWR_PUCRA_PA4_Msk                         # !< Port PA4 Pull-Up set 
PWR_PUCRA_PA3_Pos = 3
PWR_PUCRA_PA3_Msk = (0x1 << PWR_PUCRA_PA3_Pos)              # !< 0x00000008
PWR_PUCRA_PA3  = PWR_PUCRA_PA3_Msk                         # !< Port PA3 Pull-Up set 
PWR_PUCRA_PA2_Pos = 2
PWR_PUCRA_PA2_Msk = (0x1 << PWR_PUCRA_PA2_Pos)              # !< 0x00000004
PWR_PUCRA_PA2  = PWR_PUCRA_PA2_Msk                         # !< Port PA2 Pull-Up set 
PWR_PUCRA_PA1_Pos = 1
PWR_PUCRA_PA1_Msk = (0x1 << PWR_PUCRA_PA1_Pos)              # !< 0x00000002
PWR_PUCRA_PA1  = PWR_PUCRA_PA1_Msk                         # !< Port PA1 Pull-Up set 
PWR_PUCRA_PA0_Pos = 0
PWR_PUCRA_PA0_Msk = (0x1 << PWR_PUCRA_PA0_Pos)              # !< 0x00000001
PWR_PUCRA_PA0  = PWR_PUCRA_PA0_Msk                         # !< Port PA0 Pull-Up set 

# *******************  Bit definition for PWR_CR4 register  ********************/
PWR_CR4_VBRS_Pos = 9
PWR_CR4_VBRS_Msk = (0x1 << PWR_CR4_VBRS_Pos)               # !< 0x00000200*
PWR_CR4_VBRS = PWR_CR4_VBRS_Msk                          # !< VBAT Battery charging Resistor Selection*
PWR_CR4_VBE_Pos = 8
PWR_CR4_VBE_Msk = (0x1 << PWR_CR4_VBE_Pos)                # !< 0x00000100*
PWR_CR4_VBE = PWR_CR4_VBE_Msk                           # !< VBAT Battery charging Enable *
PWR_CR4_WP5_Pos = 4
PWR_CR4_WP5_Msk = (0x1 << PWR_CR4_WP5_Pos)                # !< 0x00000010*
PWR_CR4_WP5 = PWR_CR4_WP5_Msk                           # !< Wake-Up Pin 5 polarity*
PWR_CR4_WP4_Pos = 3
PWR_CR4_WP4_Msk = (0x1 << PWR_CR4_WP4_Pos)                # !< 0x00000008*
PWR_CR4_WP4 = PWR_CR4_WP4_Msk                           # !< Wake-Up Pin 4 polarity*
PWR_CR4_WP3_Pos = 2
PWR_CR4_WP3_Msk = (0x1 << PWR_CR4_WP3_Pos)                # !< 0x00000004*
PWR_CR4_WP3 = PWR_CR4_WP3_Msk                           # !< Wake-Up Pin 3 polarity*
PWR_CR4_WP2_Pos = 1
PWR_CR4_WP2_Msk = (0x1 << PWR_CR4_WP2_Pos)                # !< 0x00000002*
PWR_CR4_WP2 = PWR_CR4_WP2_Msk                           # !< Wake-Up Pin 2 polarity*
PWR_CR4_WP1_Pos = 0
PWR_CR4_WP1_Msk = (0x1 << PWR_CR4_WP1_Pos)                # !< 0x00000001*
PWR_CR4_WP1 = PWR_CR4_WP1_Msk                           # !< Wake-Up Pin 1 polarity*

# *******************  Bit definition for PWR_CR3 register  ********************/
PWR_CR3_EIWUL_Pos = 15
PWR_CR3_EIWUL_Msk = (0x1 << PWR_CR3_EIWUL_Pos)              # !< 0x00008000*
PWR_CR3_EIWUL = PWR_CR3_EIWUL_Msk                         # !< Enable Internal Wake-up line*
PWR_CR3_APC_Pos = 10
PWR_CR3_APC_Msk = (0x1 << PWR_CR3_APC_Pos)                # !< 0x00000400*
PWR_CR3_APC = PWR_CR3_APC_Msk                           # !< Apply pull-up and pull-down configuration*
PWR_CR3_RRS_Pos = 8
PWR_CR3_RRS_Msk = (0x1 << PWR_CR3_RRS_Pos)                # !< 0x00000100*
PWR_CR3_RRS = PWR_CR3_RRS_Msk                           # !< SRAM2 Retention in Stand-by mode*
PWR_CR3_EWUP5_Pos = 4
PWR_CR3_EWUP5_Msk = (0x1 << PWR_CR3_EWUP5_Pos)              # !< 0x00000010*
PWR_CR3_EWUP5 = PWR_CR3_EWUP5_Msk                         # !< Enable Wake-Up Pin 5*
PWR_CR3_EWUP4_Pos = 3
PWR_CR3_EWUP4_Msk = (0x1 << PWR_CR3_EWUP4_Pos)              # !< 0x00000008*
PWR_CR3_EWUP4 = PWR_CR3_EWUP4_Msk                         # !< Enable Wake-Up Pin 4*
PWR_CR3_EWUP3_Pos = 2
PWR_CR3_EWUP3_Msk = (0x1 << PWR_CR3_EWUP3_Pos)              # !< 0x00000004*
PWR_CR3_EWUP3 = PWR_CR3_EWUP3_Msk                         # !< Enable Wake-Up Pin 3*
PWR_CR3_EWUP2_Pos = 1
PWR_CR3_EWUP2_Msk = (0x1 << PWR_CR3_EWUP2_Pos)              # !< 0x00000002*
PWR_CR3_EWUP2 = PWR_CR3_EWUP2_Msk                         # !< Enable Wake-Up Pin 2*
PWR_CR3_EWUP1_Pos = 0
PWR_CR3_EWUP1_Msk = (0x1 << PWR_CR3_EWUP1_Pos)              # !< 0x00000001*
PWR_CR3_EWUP1 = PWR_CR3_EWUP1_Msk                         # !< Enable Wake-Up Pin 1*
PWR_CR3_EWUP_Pos = 0
PWR_CR3_EWUP_Msk = (0x1F << PWR_CR3_EWUP_Pos)              # !< 0x0000001F*
PWR_CR3_EWUP  = PWR_CR3_EWUP_Msk

# *******************  Bit definition for PWR_SCR register  ********************/
PWR_SCR_CSBF_Pos = 8
PWR_SCR_CSBF_Msk = (0x1 << PWR_SCR_CSBF_Pos)               # !< 0x00000100*
PWR_SCR_CSBF  = PWR_SCR_CSBF_Msk                          # !< Clear Stand-By Flag*
PWR_SCR_CWUF_Pos = 0
PWR_SCR_CWUF_Msk = (0x1F << PWR_SCR_CWUF_Pos)              # !< 0x0000001F*
PWR_SCR_CWUF  = PWR_SCR_CWUF_Msk                          # !< Clear Wake-up Flags *
PWR_SCR_CWUF5_Pos = 4
PWR_SCR_CWUF5_Msk = (0x1 << PWR_SCR_CWUF5_Pos)              # !< 0x00000010*
PWR_SCR_CWUF5 = PWR_SCR_CWUF5_Msk                         # !< Clear Wake-up Flag 5*
PWR_SCR_CWUF4_Pos = 3
PWR_SCR_CWUF4_Msk = (0x1 << PWR_SCR_CWUF4_Pos)              # !< 0x00000008*
PWR_SCR_CWUF4 = PWR_SCR_CWUF4_Msk                         # !< Clear Wake-up Flag 4*
PWR_SCR_CWUF3_Pos = 2
PWR_SCR_CWUF3_Msk = (0x1 << PWR_SCR_CWUF3_Pos)              # !< 0x00000004*
PWR_SCR_CWUF3 = PWR_SCR_CWUF3_Msk                         # !< Clear Wake-up Flag 3*
PWR_SCR_CWUF2_Pos = 1
PWR_SCR_CWUF2_Msk = (0x1 << PWR_SCR_CWUF2_Pos)              # !< 0x00000002*
PWR_SCR_CWUF2 = PWR_SCR_CWUF2_Msk                         # !< Clear Wake-up Flag 2*
PWR_SCR_CWUF1_Pos = 0
PWR_SCR_CWUF1_Msk = (0x1 << PWR_SCR_CWUF1_Pos)              # !< 0x00000001*
PWR_SCR_CWUF1 = PWR_SCR_CWUF1_Msk                         # !< Clear Wake-up Flag 1*

# *******************  Bit definition for PWR_CR1 register  ********************/

PWR_CR1_LPR_Pos = 14
PWR_CR1_LPR_Msk = (0x1 << PWR_CR1_LPR_Pos)                # !< 0x00004000*
PWR_CR1_LPR = PWR_CR1_LPR_Msk                           # !< Regulator low-power mode*
PWR_CR1_VOS_Pos = 9
PWR_CR1_VOS_Msk = (0x3 << PWR_CR1_VOS_Pos)                # !< 0x00000600*
PWR_CR1_VOS = PWR_CR1_VOS_Msk                           # !< VOS[1:0] bits (Regulator voltage scaling output selection)*
PWR_CR1_VOS_0 = (0x1 << PWR_CR1_VOS_Pos)                # !< 0x00000200*
PWR_CR1_VOS_1 = (0x2 << PWR_CR1_VOS_Pos)                # !< 0x00000400*
PWR_CR1_DBP_Pos = 8
PWR_CR1_DBP_Msk = (0x1 << PWR_CR1_DBP_Pos)                # !< 0x00000100*
PWR_CR1_DBP = PWR_CR1_DBP_Msk                           # !< Disable Back-up domain Protection*
PWR_CR1_LPMS_Pos = 0
PWR_CR1_LPMS_Msk = (0x7 << PWR_CR1_LPMS_Pos)               # !< 0x00000007*
PWR_CR1_LPMS  = PWR_CR1_LPMS_Msk                          # !< Low-power mode selection field*
PWR_CR1_LPMS_STOP0 = (0x00000000)                            # !< Stop 0 mode*
PWR_CR1_LPMS_STOP1_Pos = 0
PWR_CR1_LPMS_STOP1_Msk = (0x1 << PWR_CR1_LPMS_STOP1_Pos)         # !< 0x00000001*
PWR_CR1_LPMS_STOP1 = PWR_CR1_LPMS_STOP1_Msk                    # !< Stop 1 mode*
PWR_CR1_LPMS_STOP2_Pos = 1
PWR_CR1_LPMS_STOP2_Msk = (0x1 << PWR_CR1_LPMS_STOP2_Pos)         # !< 0x00000002*
PWR_CR1_LPMS_STOP2 = PWR_CR1_LPMS_STOP2_Msk                    # !< Stop 2 mode*
PWR_CR1_LPMS_STANDBY_Pos = 0
PWR_CR1_LPMS_STANDBY_Msk = (0x3 << PWR_CR1_LPMS_STANDBY_Pos)       # !< 0x00000003*
PWR_CR1_LPMS_STANDBY = PWR_CR1_LPMS_STANDBY_Msk                  # !< Stand-by mode*
PWR_CR1_LPMS_SHUTDOWN_Pos = 2
PWR_CR1_LPMS_SHUTDOWN_Msk = (0x1 << PWR_CR1_LPMS_SHUTDOWN_Pos)      # !< 0x00000004*
PWR_CR1_LPMS_SHUTDOWN = PWR_CR1_LPMS_SHUTDOWN_Msk                 # !< Shut-down mode*

# https://community.st.com/t5/stm32-mcus-embedded-software/how-to-enter-standby-or-shutdown-mode-on-stm32/td-p/145849
#  // Configure wake-up features
#  // WKUP1(PA0) - active high, WKUP4(PA2) - active low, pull-up
#  PWR->PUCRA = PWR_PUCRA_PA2; // Set pull-ups for standby modes
#  PWR->CR4 = PWR_CR4_WP4; // Set wakeup pins' polarity to low level
#  PWR->CR3 = PWR_CR3_APC | PWR_CR3_EWUP4 | PWR_CR3_EWUP1; // Enable pin pull configurations and wakeup pins
#  PWR->SCR = PWR_SCR_CWUF; // Clear wakeup flags
#  
#  // Configure MCU low-power mode for CPU deep sleep mode
#  PWR->CR1 |= PWR_CR1_LPMS_STANDBY; // PWR_CR1_LPMS_SHUTDOWN
#  (void)PWR->CR1; // Ensure that the previous PWR register operations have been completed
#  
#  // Configure CPU core
#  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; // Enable CPU deep sleep mode
# #ifdef NDEBUG
#  DBGMCU->CR = 0; // Disable debug, trace and IWDG in low-power modes
# #endif
#  
#  // Enter low-power mode
#  for (;;) {
#   __DSB();
#   __WFI();
#  }

import stm
import machine
import pyb

# Configure wake-up features
# WKUP1(PA0) - active high, WKUP4(PA2) - active low, pull-up
#
# Set pull-ups for standby modes
stm.mem32[stm.PWR_PUCRA] = PWR_PUCRA_PA2
# Set wakeup pins' polarity to low level
stm.mem32[stm.PWR_CR4] = PWR_CR4_WP4
# Enable pin pull configurations and wakeup pins
stm.mem32[stm.PWR_CR3] = PWR_CR3_APC | PWR_CR3_EWUP4 | PWR_CR3_EWUP1
# Clear wakeup flags
stm.mem32[stm.PWR_SCR] = PWR_SCR_CWUF


# Configure MCU low-power mode for CPU deep sleep mode
#
stm.mem32[stm.PWR_CR1] |= PWR_CR1_LPMS_STANDBY # PWR_CR1_LPMS_SHUTDOWN
# Ensure that the previous PWR register operations have been completed
fake = stm.mem32[stm.PWR_CR1]

# Configure CPU core
#
# Enable CPU deep sleep mode
stm.mem32[SCB_SCR] |= SCB_SCR_SLEEPDEEP_Msk
# Disable debug, trace and IWDG in low-power modes
# stm.mem32[stm.DBGMCU_CR] = 0

# pyb.standby()
pyb.wfi()

The board doesn't react when I pull-up PA2 (pull-downed with or without a resistor).

Then I had a look in HAL form STM, and wrote this piece of code:

import stm, machine, pyb


# https://libopencm3.org/docs/latest/stm324/html/group__cm__scb__registers.html#ga046351cf4159d1e8953730326c31ec5c
# ******************* memorymap.h
PPBI_BASE = 0xE0000000
SCS_BASE =  PPBI_BASE + 0xE000
SCB_BASE = SCS_BASE + 0x0D00
SCB_SCR = SCB_BASE + 0x10

# STM32CubeL4/Drivers/CMSIS/Include/core_cm3.h
#
# *SCB System Control Register Definitions*
SCB_SCR_SEVONPEND_Pos = 4                                            # !< SCB SCR: SEVONPEND Position
SCB_SCR_SEVONPEND_Msk = (1 << SCB_SCR_SEVONPEND_Pos)                 # !< SCB SCR: SEVONPEND Mask

SCB_SCR_SLEEPDEEP_Pos = 2                                            # !< SCB SCR: SLEEPDEEP Position
SCB_SCR_SLEEPDEEP_Msk = (1 << SCB_SCR_SLEEPDEEP_Pos)                 # !< SCB SCR: SLEEPDEEP Mask

SCB_SCR_SLEEPONEXIT_Pos = 1                                            # !< SCB SCR: SLEEPONEXIT Position
SCB_SCR_SLEEPONEXIT_Msk = (1 << SCB_SCR_SLEEPONEXIT_Pos)               # !< SCB SCR: SLEEPONEXIT Mask


# CMSIS/STM32L4xx/Include/stm32l452xx.h
# /********************  Bit definition for PWR_SR1 register  ********************/
PWR_SR1_WUFI_Pos = 15
PWR_SR1_WUFI_Msk = (0x1 << PWR_SR1_WUFI_Pos)               # !< 0x00008000 */
PWR_SR1_WUFI = PWR_SR1_WUFI_Msk                          # !< Wake-Up Flag Internal */
PWR_SR1_SBF_Pos = 8
PWR_SR1_SBF_Msk = (0x1 << PWR_SR1_SBF_Pos)                # !< 0x00000100 */
PWR_SR1_SBF  = PWR_SR1_SBF_Msk                           # !< Stand-By Flag */
PWR_SR1_WUF_Pos = 0
PWR_SR1_WUF_Msk = (0x1F << PWR_SR1_WUF_Pos)               # !< 0x0000001F */
PWR_SR1_WUF  = PWR_SR1_WUF_Msk                           # !< Wake-up Flags */
PWR_SR1_WUF5_Pos = 4
PWR_SR1_WUF5_Msk = (0x1 << PWR_SR1_WUF5_Pos)               # !< 0x00000010 */
PWR_SR1_WUF5 = PWR_SR1_WUF5_Msk                          # !< Wake-up Flag 5 */
PWR_SR1_WUF4_Pos = 3
PWR_SR1_WUF4_Msk = (0x1 << PWR_SR1_WUF4_Pos)               # !< 0x00000008 */
PWR_SR1_WUF4 = PWR_SR1_WUF4_Msk                          # !< Wake-up Flag 4 */
PWR_SR1_WUF3_Pos = 2
PWR_SR1_WUF3_Msk = (0x1 << PWR_SR1_WUF3_Pos)               # !< 0x00000004 */
PWR_SR1_WUF3 = PWR_SR1_WUF3_Msk                          # !< Wake-up Flag 3 */
PWR_SR1_WUF2_Pos = 1
PWR_SR1_WUF2_Msk = (0x1 << PWR_SR1_WUF2_Pos)               # !< 0x00000002 */
PWR_SR1_WUF2 = PWR_SR1_WUF2_Msk                          # !< Wake-up Flag 2 */
PWR_SR1_WUF1_Pos = 0
PWR_SR1_WUF1_Msk = (0x1 << PWR_SR1_WUF1_Pos)               # !< 0x00000001 */
PWR_SR1_WUF1 = PWR_SR1_WUF1_Msk

# *******************  Bit definition for PWR_SCR register  ********************/
PWR_SCR_CSBF_Pos = 8
PWR_SCR_CSBF_Msk = (0x1 << PWR_SCR_CSBF_Pos)               # !< 0x00000100*
PWR_SCR_CSBF  = PWR_SCR_CSBF_Msk                          # !< Clear Stand-By Flag*
PWR_SCR_CWUF_Pos = 0
PWR_SCR_CWUF_Msk = (0x1F << PWR_SCR_CWUF_Pos)              # !< 0x0000001F*
PWR_SCR_CWUF  = PWR_SCR_CWUF_Msk                          # !< Clear Wake-up Flags *
PWR_SCR_CWUF5_Pos = 4
PWR_SCR_CWUF5_Msk = (0x1 << PWR_SCR_CWUF5_Pos)              # !< 0x00000010*
PWR_SCR_CWUF5 = PWR_SCR_CWUF5_Msk                         # !< Clear Wake-up Flag 5*
PWR_SCR_CWUF4_Pos = 3
PWR_SCR_CWUF4_Msk = (0x1 << PWR_SCR_CWUF4_Pos)              # !< 0x00000008*
PWR_SCR_CWUF4 = PWR_SCR_CWUF4_Msk                         # !< Clear Wake-up Flag 4*
PWR_SCR_CWUF3_Pos = 2
PWR_SCR_CWUF3_Msk = (0x1 << PWR_SCR_CWUF3_Pos)              # !< 0x00000004*
PWR_SCR_CWUF3 = PWR_SCR_CWUF3_Msk                         # !< Clear Wake-up Flag 3*
PWR_SCR_CWUF2_Pos = 1
PWR_SCR_CWUF2_Msk = (0x1 << PWR_SCR_CWUF2_Pos)              # !< 0x00000002*
PWR_SCR_CWUF2 = PWR_SCR_CWUF2_Msk                         # !< Clear Wake-up Flag 2*
PWR_SCR_CWUF1_Pos = 0
PWR_SCR_CWUF1_Msk = (0x1 << PWR_SCR_CWUF1_Pos)              # !< 0x00000001*
PWR_SCR_CWUF1 = PWR_SCR_CWUF1_Msk

# /********************  Bit definition for PWR_CR3 register  ********************/
PWR_CR3_EWUP5_Pos = 4
PWR_CR3_EWUP5_Msk = (0x1 << PWR_CR3_EWUP5_Pos)        # !< 0x00000010
PWR_CR3_EWUP5     = PWR_CR3_EWUP5_Msk                 # !< Enable Wake-Up Pin 5
PWR_CR3_EWUP4_Pos = 3
PWR_CR3_EWUP4_Msk = (0x1 << PWR_CR3_EWUP4_Pos)        # !< 0x00000008
PWR_CR3_EWUP4     = PWR_CR3_EWUP4_Msk                 # !< Enable Wake-Up Pin 4
PWR_CR3_EWUP3_Pos = 2
PWR_CR3_EWUP3_Msk = (0x1 << PWR_CR3_EWUP3_Pos)        # !< 0x00000004
PWR_CR3_EWUP3     = PWR_CR3_EWUP3_Msk                 # !< Enable Wake-Up Pin 3
PWR_CR3_EWUP2_Pos = 1
PWR_CR3_EWUP2_Msk = (0x1 << PWR_CR3_EWUP2_Pos)        # !< 0x00000002
PWR_CR3_EWUP2     = PWR_CR3_EWUP2_Msk                 # !< Enable Wake-Up Pin 2
PWR_CR3_EWUP1_Pos = 0
PWR_CR3_EWUP1_Msk = (0x1 << PWR_CR3_EWUP1_Pos)        # !< 0x00000001
PWR_CR3_EWUP1     = PWR_CR3_EWUP1_Msk                 # !< Enable Wake-Up Pin 1
PWR_CR3_EWUP_Pos  =  0
PWR_CR3_EWUP_Msk  = (0x1F << PWR_CR3_EWUP_Pos)        # !< 0x0000001F
PWR_CR3_EWUP      = PWR_CR3_EWUP_Msk 

# /********************  Bit definition for PWR_CR4 register  ********************/
PWR_CR4_WP5_Pos = 4
PWR_CR4_WP5_Msk = (0x1 << PWR_CR4_WP5_Pos)          # !< 0x00000010
PWR_CR4_WP5     = PWR_CR4_WP5_Msk                   # !< Wake-Up Pin 5 polarity
PWR_CR4_WP4_Pos = 3
PWR_CR4_WP4_Msk = (0x1 << PWR_CR4_WP4_Pos)          # !< 0x00000008
PWR_CR4_WP4     = PWR_CR4_WP4_Msk                   # !< Wake-Up Pin 4 polarity
PWR_CR4_WP3_Pos = 2
PWR_CR4_WP3_Msk = (0x1 << PWR_CR4_WP3_Pos)          # !< 0x00000004
PWR_CR4_WP3     = PWR_CR4_WP3_Msk                   # !< Wake-Up Pin 3 polarity
PWR_CR4_WP2_Pos = 1
PWR_CR4_WP2_Msk = (0x1 << PWR_CR4_WP2_Pos)          # !< 0x00000002
PWR_CR4_WP2     = PWR_CR4_WP2_Msk                   # !< Wake-Up Pin 2 polarity
PWR_CR4_WP1_Pos = 0
PWR_CR4_WP1_Msk = (0x1 << PWR_CR4_WP1_Pos)          # !< 0x00000001
PWR_CR4_WP1     = PWR_CR4_WP1_Msk                   # !< Wake-Up Pin 1 polarity

# *******************  Bit definition for PWR_CR1 register  ********************/
PWR_CR1_LPR_Pos = 14
PWR_CR1_LPR_Msk = (0x1 << PWR_CR1_LPR_Pos)                # !< 0x00004000*
PWR_CR1_LPR = PWR_CR1_LPR_Msk                           # !< Regulator low-power mode*
PWR_CR1_VOS_Pos = 9
PWR_CR1_VOS_Msk = (0x3 << PWR_CR1_VOS_Pos)                # !< 0x00000600*
PWR_CR1_VOS = PWR_CR1_VOS_Msk                           # !< VOS[1:0] bits (Regulator voltage scaling output selection)*
PWR_CR1_VOS_0 = (0x1 << PWR_CR1_VOS_Pos)                # !< 0x00000200*
PWR_CR1_VOS_1 = (0x2 << PWR_CR1_VOS_Pos)                # !< 0x00000400*
PWR_CR1_DBP_Pos = 8
PWR_CR1_DBP_Msk = (0x1 << PWR_CR1_DBP_Pos)                # !< 0x00000100*
PWR_CR1_DBP = PWR_CR1_DBP_Msk                           # !< Disable Back-up domain Protection*
PWR_CR1_LPMS_Pos = 0
PWR_CR1_LPMS_Msk = (0x7 << PWR_CR1_LPMS_Pos)               # !< 0x00000007*
PWR_CR1_LPMS  = PWR_CR1_LPMS_Msk                          # !< Low-power mode selection field*
PWR_CR1_LPMS_STOP0 = (0x00000000)                            # !< Stop 0 mode*
PWR_CR1_LPMS_STOP1_Pos = 0
PWR_CR1_LPMS_STOP1_Msk = (0x1 << PWR_CR1_LPMS_STOP1_Pos)         # !< 0x00000001*
PWR_CR1_LPMS_STOP1 = PWR_CR1_LPMS_STOP1_Msk                    # !< Stop 1 mode*
PWR_CR1_LPMS_STOP2_Pos = 1
PWR_CR1_LPMS_STOP2_Msk = (0x1 << PWR_CR1_LPMS_STOP2_Pos)         # !< 0x00000002*
PWR_CR1_LPMS_STOP2 = PWR_CR1_LPMS_STOP2_Msk                    # !< Stop 2 mode*
PWR_CR1_LPMS_STANDBY_Pos = 0
PWR_CR1_LPMS_STANDBY_Msk = (0x3 << PWR_CR1_LPMS_STANDBY_Pos)       # !< 0x00000003*
PWR_CR1_LPMS_STANDBY = PWR_CR1_LPMS_STANDBY_Msk                  # !< Stand-by mode*
PWR_CR1_LPMS_SHUTDOWN_Pos = 2
PWR_CR1_LPMS_SHUTDOWN_Msk = (0x1 << PWR_CR1_LPMS_SHUTDOWN_Pos)      # !< 0x00000004*
PWR_CR1_LPMS_SHUTDOWN = PWR_CR1_LPMS_SHUTDOWN_Msk                 # !< Shut-down mode*

# STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
PWR_FLAG_WU = PWR_SR1_WUF
PWR_WUP_POLARITY_SHIFT = 0x05

PWR_WAKEUP_PIN1 = PWR_CR3_EWUP1  # !< Wakeup pin 1 (with high level polarity)
PWR_WAKEUP_PIN2 = PWR_CR3_EWUP2  # !< Wakeup pin 2 (with high level polarity)
PWR_WAKEUP_PIN3 = PWR_CR3_EWUP3  # !< Wakeup pin 3 (with high level polarity)
PWR_WAKEUP_PIN4 = PWR_CR3_EWUP4  # !< Wakeup pin 4 (with high level polarity)
PWR_WAKEUP_PIN5 = PWR_CR3_EWUP5  # !< Wakeup pin 5 (with high level polarity)
PWR_WAKEUP_PIN1_HIGH = PWR_CR3_EWUP1  # !< Wakeup pin 1 (with high level polarity)
PWR_WAKEUP_PIN2_HIGH = PWR_CR3_EWUP2  # !< Wakeup pin 2 (with high level polarity)
PWR_WAKEUP_PIN3_HIGH = PWR_CR3_EWUP3  # !< Wakeup pin 3 (with high level polarity)
PWR_WAKEUP_PIN4_HIGH = PWR_CR3_EWUP4  # !< Wakeup pin 4 (with high level polarity)
PWR_WAKEUP_PIN5_HIGH = PWR_CR3_EWUP5  # !< Wakeup pin 5 (with high level polarity)
PWR_WAKEUP_PIN1_LOW = ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) # !< Wakeup pin 1 (with low level polarity)
PWR_WAKEUP_PIN2_LOW = ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) # !< Wakeup pin 2 (with low level polarity)
PWR_WAKEUP_PIN3_LOW = ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) # !< Wakeup pin 3 (with low level polarity)
PWR_WAKEUP_PIN4_LOW = ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) # !< Wakeup pin 4 (with low level polarity)
PWR_WAKEUP_PIN5_LOW = ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) # !< Wakeup pin 5 (with low level polarity)



# STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
# /**
#   * @brief Enable the WakeUp PINx functionality.
#   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
#   *         This parameter can be one of the following legacy values which set the default polarity
#   *         i.e. detection on high level (rising edge):
#   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
#   *
#   *         or one of the following value where the user can explicitly specify the enabled pin and
#   *         the chosen polarity:
#   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
#   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
#   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
#   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
#   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
#   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
#   * @retval None
#   */
# void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
# {
#   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
# 
#   /* Specifies the Wake-Up pin polarity for the event detection
#     (rising or falling edge) */
#   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
# 
#   /* Enable wake-up pin */
#   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
# 
# 
# }
def pwr_enable_wakeup_pin(wake_up_pin_polarity):
    modify_reg(stm.PWR_CR4, (PWR_CR3_EWUP & wake_up_pin_polarity), (wake_up_pin_polarity >> PWR_WUP_POLARITY_SHIFT))
    stm.mem32[stm.PWR_CR3] |= (PWR_CR3_EWUP & wake_up_pin_polarity)



# STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
# /**
#   * @brief Enter Standby mode.
#   * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
#   *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
#   *        in which case the regulator is in low-power mode.
#   *        SRAM1 and register contents are lost except for registers in the Backup domain and
#   *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
#   *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
#   *        to set RRS bit.
#   *        The BOR is available.
#   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
#   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
#   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
#   *        same.
#   *        These states are effective in Standby mode only if APC bit is set through
#   *        HAL_PWREx_EnablePullUpPullDownConfig() API.
#   * @retval None
#   */
# void HAL_PWR_EnterSTANDBYMode(void)
# { 
#   /* Set Stand-by mode */
#   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
#     
#   /* Set SLEEPDEEP bit of Cortex System Control Register */
#   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
#         
# /* This option is used to ensure that store operations are completed */
# #if defined ( __CC_ARM)
#   __force_stores();
# #endif
#   /* Request Wait For Interrupt */
#   __WFI();
# }   
def pwr_enter_standby_mode():
    modify_reg(stm.PWR_CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY)
    stm.mem32[SCB_SCR] |= SCB_SCR_SLEEPDEEP_Msk


# STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
# /** @brief  Clear a specific PWR flag.
#   * @param  __FLAG__ specifies the flag to clear.
#   *          This parameter can be one of the following values:
#   *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
#   *                  was received from the WKUP pin 1.
#   *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
#   *                  was received from the WKUP pin 2.
#   *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
#   *                  was received from the WKUP pin 3.
#   *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
#   *                  was received from the WKUP pin 4.
#   *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
#   *                  was received from the WKUP pin 5.
#   *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
#   *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
#   *                  entered Standby mode.
#   * @retval None
#   */
# #define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
#                                          (PWR->SCR  = (__FLAG__)) :\
#                                          (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
def pwr_clear_flag(__FLAG__):
    if __FLAG__ == PWR_FLAG_WU:
        stm.mem32[stm.PWR_SCR] = __FLAG__
    else:
        stm.mem32[stm.PWR_SCR] = (1 << ((__FLAG__) & 31))


# CMSIS/STM32L4xx/Include/stm32l4xx.h
# #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
def modify_reg(reg, clearmask, setmask):
    stm.mem32[reg] = (((stm.mem32[reg]) & (~(clearmask))) | (setmask))
    



pwr_enable_wakeup_pin(PWR_WAKEUP_PIN4)
# PWR_FLAG clearing must be done after configuration
# https://community.st.com/t5/stm32-mcus-products/proper-standby-mode-enter-and-exit/m-p/74176/highlight/true#M7407
pwr_clear_flag(PWR_FLAG_WU)
pwr_enter_standby_mode()

But it still doesn't react on PA2 pulled-up, with or without pull-down resistor.
Strangely, from this one, I have a prompt from mpremote once the code is ran, but unresponsive. If I click on NRST button, it boots from pwr reset, not from deepsleep.

I am largely beyond my skills here, and any support would be much more appreciated.

Thanks an lot,

Eric.