PIO scripts on RP2350

[peterhinch]

I have written an SPI slave using the PIO and DMA, which works on the Pico but fails on the Pico 2.

I reduced it down to the script below which simply counts clock pulses while CS/ is low. Sending a clock with CS/ high terminates the SM (label done), which places a number in the RX FIFO. A hard interrupt triggered by CS/ going high causes the data to be read - but not on RP2350 where the assert statement bombs.

Am I missing some change in the PIO design?

# Test script counts CLK pulses while CS/ is active. Runs on RP2040 but not on RP2350.
# Links (GPIO nos).
# 0 - 19 MOSI
# 1 - 18 CLK
# 2 - 17 CS/

import rp2
from machine import Pin, SPI
import asyncio

@rp2.asm_pio(autopush=True)
def spi_count():
    wrap_target()
    wait(1, pins, 2)  # CS/ False
    wait(0, pins, 2)  # CS/ True
    set(x, 0)
    label("bit")
    wait(0, pins, 1)
    wait(1, pins, 1)
    jmp(pin, "done")  # Master resets slave by sending  byte with CS high
    jmp(x_dec, "bit")  # Post decrement.
    jmp("bit")
    label("done")
    in_(x, 32)
    wrap()

# pin numbers (offset from start_pin)
# 0 MOSI
# 1 Clk
# 2 CS\

class SpiTest:

    def __init__(self, start_pin=0, sm_num=0):
        self._tsf = asyncio.ThreadSafeFlag()
        csn = Pin(start_pin + 2, Pin.IN)  # IRQ occurs at end of transfer
        csn.irq(self._done, trigger=Pin.IRQ_RISING, hard=True)
        self._sm1 = rp2.StateMachine(
            sm_num,
            spi_count,
            in_base=Pin(start_pin),
            jmp_pin=csn,
        )
        self._sm1.active(1)

    async def read_into(self):
        await self._tsf.wait()  # Wait for CS/ high (master signals transfer complete)
        assert self._sm1.rx_fifo(), "Rx fifo is empty."
        return self._sm1.get()

    def _done(self, _):  # ISR for CS/ +ve going edge
        self._tsf.set()


async def receive():
    piospi = SpiTest()
    nb = await piospi.read_into()
    print(f"Result {nb} expect 4294965248")  

async def test():
    cs = Pin(17, Pin.OUT, value=1)
    rt = asyncio.create_task(receive())
    await asyncio.sleep_ms(0)  # Ensure receive task is running
    spi = SPI(0, sck=Pin(18, Pin.OUT), mosi=Pin(19, Pin.OUT), miso=Pin(16, Pin.IN))
    cs(0)
    spi.write(bytearray(256))  # Create 256 clock pulses
    cs(1)
    spi.write(b'\xff')  # Reset SM
    await asyncio.sleep_ms(500)

asyncio.run(test())

[mendenm]

You might try running my data analyzer at https://github.com/mendenm/rp2_micropython_tricks/blob/main/data_compressing_analyzer.py to see what the pins are doing. It’s quite useful to let a pico self-analyze.

[mendenm]

Have you tried lowering the SPI clock frequency, just to make sure there isn’t something slightly different about the pin drive and its compatibility with your wiring?

[peterhinch]

Yes. This is proving had to pin down. Each time I think I've identified the problem and produce a minimal repro - only to find the script runs on both chips.

[mendenm]

Have you tried shifting the cs pin off of 17? Weirdly, these processors assign a cs pin to the SPI, which you are using, and maybe there’s a driver or hardware difference on that. Try a pin that isn’t part of the SPI block.

[peterhinch]

Nice try, but no banana. I've also tried SoftSPI.

[peterhinch]

I have finally achieved a fairly minimal repro, and raised #17047.