DMA interrupts

[AeroSynth]

I would like to set up a DMA transfer between memory and some external peripheral on a RP2 (Pico).
I want to use one DMA channel and ping-pong between two memory buffers of fixed length so that while one is being transferred to the peripheral (e.g. PWM or PIO) via DMA, the other is available for signal processing or updating. The DMA cycle time is controlled by a timer (sample rate of audio).
To do this, I need an interrupt after the buffer has been transferred to tell me when to the DMA to change the source address to the other buffer that is finished being processed. So the two data buffers "ping-pong"-- whilst one is being transferred, the other is available for processing.

I can do this easily in C and it works very well (like the example on page 99 of the RP2040 data sheet). Is there a way to set up a DMA-transfer complete interrupt handler in MicroPython? I suppose I could manually program the peripherals and the NVIC registers but was wondering if there was an alternative. I did review https://github.com/rkompass/RPi2040_mPy/tree/main/rp2_dma excellent DMA helper utilities and that is a good start.

Note that I can use a second DMA to set up a ping pong scheme and it may be faster, but I still need an interrupt to know when one of the channels is idle so I know when to update the buffer (I don't want to poll).

[rkompass]

Thank you.
This is the question I also still have to ask. So I'm very interested in answers/solutions, although I assume there are no straightforward ones.

Note that with the above mentioned dma class you do not have to ping pong. With
dma = RP2_Dma((snd_arr, snd_arr2), pwm, cycle=DMA_Cycle_Src, dreq=TREQ_Timer0)
automatically a second DMA is set up so as to act as a master that cyclically reconfigures the slave to transfer from the other array.
Which results in the same behaviour like ping ponging but also allows to cycle through 4 source arrays, for example.

A workaround would be a timer or async sleep that resumes activity just in time to wait say the last 5% of transfer time to finish by
repeatedly checking (polling) dma.transfer_count(), thus synchronizing to the actual rate of switching arrays.

I agree that polling is an undesirable solution. Perhaps a minimal polling is viable like waiting/sleeping a crude estimate of 75% the single array transfer time, then checking actual transfer count, computing the error and waiting/sleeping for a better estimated rest of time.
But still the interrupt question is open because there are sources that are unpredictable like UART or PIO.

I plan to extend my class to include transfers of ADC, I2C and SPI and then checking if the same API may be applied for other hardware like the pyboard. I had the impression that agreement on a certain API was one of the stumbling blocks of getting a universal dma functionality in uPy.

[AeroSynth]

Can't use asynchio or threading. Polling is not an option. Must be very deterministic.
The method in your class for ping-pong should work as long as I can generate interrupts from each channel. I'll try this using a viper method and let you know how it works out. May take some time though...

[rkompass]

With a new member function

    def set_irq(self, enable, irq_line=0):  # we have two dma interrpupts: irq_line: 0 -> DMA_IRQ0, 1 -> DMA_IRQ0
        dma_addr = 0x50000000 + self.chan * 0x40
        machine.mem32[0x5000040c + bool(irq_line)*0x10] = 1<<self.chan # clear any preceding pending interrupt
        if enable:                                   # set 1<<self.chan bit in INTE0 or INTE1, depending on irq_line
            machine.mem32[0x50000404 + bool(irq_line)*0x10] |= 1 << self.chan
            machine.mem32[dma_addr+16] &= 0xffdfffff # clear bit 21 (IRQ_QUIET) of CTRL in Alias 1 (without triggering),
        else:                                        # now every finished transfer will raise an interrupt
            machine.mem32[0x50000404 + bool(irq_line)*0x10] &= 0xffffffff ^ (1<<self.chan) # clear 1<<self.chan bit 
            machine.mem32[dma_addr+16] |= 0x200000   # reset bit 21 (IRQ_QUIET) of CTRL

of the dma class and

dma = RP2_Dma(snd_arr, pwm, cycle=DMA_Cycle_Src, dreq=TREQ_Timer0)     # but can also use a single array as source; synchonize with dma timer 0
dma.timer(0, freq=44109)                                               # Set dma timer 0 to 40109 Hz.
dma.set_irq(True, 0)

Timer(period=8000, mode=Timer.ONE_SHOT, callback=lambda t:dma.deinit())  # stop the dma automatically after 9 seconds
print('dma.busy():', dma.busy(), '    pwm.busy():', pwm.busy(), '   interrupt pending:', machine.mem32[0x5000040c])
dma.start()

for _ in range(12):
    print('dma.busy():', dma.busy(), '    pwm.busy():', pwm.busy(), '   interrupt pending:', machine.mem32[0x5000040c])
    sleep(1)
pwm.deinit()
print('dma.busy():', dma.busy(), '    pwm.busy():', pwm.busy())

in the end of rp2_dma_test5.py I get

Sine wave of 220.54 Hz with 200 sampling points at 44109.00 Hz sample rate
dma.busy(): False     pwm.busy(): True    interrupt pending: 0
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): True     pwm.busy(): True    interrupt pending: 1
dma.busy(): False     pwm.busy(): True    interrupt pending: 1
dma.busy(): False     pwm.busy(): True    interrupt pending: 1
dma.busy(): False     pwm.busy(): True    interrupt pending: 1
dma.busy(): False     pwm.busy(): True    interrupt pending: 1
dma.busy(): False     pwm.busy(): False

So the interrupts are there.
But nothing tells Micropython (how) to react to them. So these interrupts are ignored.
We should ask the experts for providing a way to register ISRs for functionality that is not yet represented in uPy internally.