pulp-platform

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315 repositories

magia-sdk
Public
C
•4•4•0•0•Updated Sep 18, 2025Sep 18, 2025
FlooNoC
Public
A Fast, Low-Overhead On-chip Network
SystemVerilog
•
Apache License 2.0
•44•226•21•6•Updated Sep 18, 2025Sep 18, 2025
tech_cells_generic
Public
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
SystemVerilog
•
Other
•35•65•2•6•Updated Sep 18, 2025Sep 18, 2025
common_cells
Public
Common SystemVerilog components
SystemVerilog
•
Other
•178•656•33•10•Updated Sep 18, 2025Sep 18, 2025
AraXL
Public
Assembly
•
Other
•0•0•0•0•Updated Sep 18, 2025Sep 18, 2025
Deeploy
Public
DNN Compiler for Heterogeneous SoCs
mcu tinyml ml-compiler
Python
•18•46•8•4•Updated Sep 18, 2025Sep 18, 2025
cluster_interconnect
Public
SystemVerilog
•
Other
•15•15•1•3•Updated Sep 18, 2025Sep 18, 2025
cheshire
Public
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
asic riscv systemverilog rtl-design fpga simulation
Verilog
•
Other
•78•283•14•24•Updated Sep 18, 2025Sep 18, 2025
snitch_cluster
Public
An energy-efficient RISC-V floating-point compute cluster.
C
•
Apache License 2.0
•85•108•22•8•Updated Sep 17, 2025Sep 17, 2025
cva6-sdk
Public
CVA6 SDK containing RISC-V tools and Buildroot
Makefile
•82•2•0•3•Updated Sep 17, 2025Sep 17, 2025
u-boot
Public
Unofficial development fork of U-Boot
C
•15•0•0•0•Updated Sep 17, 2025Sep 17, 2025
pulp_cluster
Public
The multi-core cluster of a PULP system.
SystemVerilog
•
Other
•31•108•5•2•Updated Sep 17, 2025Sep 17, 2025
mempool
Public
A 256-RISC-V-core system with low-latency access into shared L1 memory.
asic risc-v manycore
C
•
Apache License 2.0
•56•304•3•5•Updated Sep 17, 2025Sep 17, 2025
cva6
Public
This is the fork of CVA6 intended for PULP development.
Assembly
•
Other
•830•22•1•7•Updated Sep 16, 2025Sep 16, 2025
spatz
Public
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
C
•
Apache License 2.0
•27•117•1•2•Updated Sep 16, 2025Sep 16, 2025
picobello
Public
whatever it means
C
•
Other
•6•9•7•0•Updated Sep 16, 2025Sep 16, 2025
opensbi
Public
RISC-V Open Source Supervisor Binary Interface
C
•
Other
•608•0•0•0•Updated Sep 16, 2025Sep 16, 2025
llvm-project
Public
C++
•15k•12•7•1•Updated Sep 16, 2025Sep 16, 2025
axi
Public
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite
SystemVerilog
•
Other
•311•1.4k•48•16•Updated Sep 15, 2025Sep 15, 2025
riscv-dbg
Public
RISC-V Debug Support for our PULP RISC-V Cores
riscv debug
SystemVerilog
•
Other
•86•271•35•7•Updated Sep 15, 2025Sep 15, 2025
redmule
Public
SystemVerilog
•
Other
•18•76•2•3•Updated Sep 15, 2025Sep 15, 2025
ManyRVData
Public
0•0•0•1•Updated Sep 14, 2025Sep 14, 2025
axi_riscv_atomics
Public
AXI Adapter(s) for RISC-V Atomic Operations
SystemVerilog
•
Other
•21•66•1•2•Updated Sep 12, 2025Sep 12, 2025
iDMA
Public
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
SystemVerilog
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Other
•37•183•11•4•Updated Sep 12, 2025Sep 12, 2025
hci
Public
Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
SystemVerilog
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Other
•17•14•5•5•Updated Sep 12, 2025Sep 12, 2025
MAGIA
Public
Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
SystemVerilog
•
Apache License 2.0
•3•7•1•1•Updated Sep 11, 2025Sep 11, 2025
regression_tests
Public
C
•19•10•3•3•Updated Sep 10, 2025Sep 10, 2025
fpu_div_sqrt_mvp
Public
[UNRELEASED] FP div/sqrt unit for transprecision
SystemVerilog
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Other
•17•24•13•5•Updated Sep 9, 2025Sep 9, 2025
obi
Public
OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
SystemVerilog
•
Other
•9•18•1•7•Updated Sep 9, 2025Sep 9, 2025
bender
Public
A dependency management tool for hardware projects.
Rust
•
Apache License 2.0
•52•321•28•9•Updated Sep 9, 2025Sep 9, 2025