Merge pull request #906 from os-fpga/checker_handle_disabled_RAM_clock_inputs_E3235

checker: handle disabled RAM clock-inputs EDA-3235

Author: serge-dsa

planning/src/RS/rsCheck.cpp

@@ -125,7 +125,7 @@ bool do_check_blif(CStr cfn,
     if (numWarn)
       lprintf("  # WARNINGS= %u", numWarn);
     lputs();
-    if (numWarn or ::getenv("pln_always_write_blif")) {
+    if (0&& (numWarn or ::getenv("pln_always_write_blif"))) {
       std::filesystem::path full_path{bfile.fnm_};
       std::filesystem::path base_path = full_path.filename();
       std::string base = base_path.string();
@@ -221,9 +221,13 @@ bool do_cleanup_blif(CStr cfn, vector<uspair>& corrected) {
 
       // -- 1. add prefix 'orig_' to the original BLIF
       {
-        string newName = str::concat("orig_", cfn);
-        filesystem::path newPath{newName};
+        // string newName = str::concat("orig_", cfn);
         filesystem::path oldPath{cfn};
+        filesystem::path newPath = oldPath.lexically_normal();
+        assert(newPath.has_filename());
+        string path_fn = newPath.filename().string();
+        string new_fn = str::concat("orig_", path_fn);
+        newPath.replace_filename(new_fn);
         error_code ec;
         filesystem::rename(oldPath, newPath, ec);
         if (ec) {
@@ -234,6 +238,7 @@ bool do_cleanup_blif(CStr cfn, vector<uspair>& corrected) {
             << "       ERROR: " << ec.message() << '\n' << endl;
         }
         else if (tr >= 3) {
+          string newName = newPath.string();
           lprintf("[PLANNER BLIF-CLEANER] :   original BLIF saved as '%s'\n",
                   newName.c_str());
         }

planning/src/file_io/pln_blif_file.cpp

@@ -1506,6 +1506,55 @@ bool BLIF_file::createNodes() noexcept {
     nd.id_ = i;
   }
 
+  // possibly adjust "clockness" flag of some RAM18KX2 clock inputs.
+  // RAM18KX2 instances may have unused halves with clock inputs
+  // (CLK_A1/2, CLK_B1/2) connected to $false.
+  // This seems to be allowed. EDA-3235.
+  uint RAM18KX2_cnt_total = 0, RAM18KX2_cnt_disabled = 0;
+  for (BNode* x : fabricRealNodes_) {
+    BNode& nd = *x;
+    assert(not nd.isTopPort());
+    assert(not nd.isVirtualMog());
+    if (nd.ptype_ != prim::TDP_RAM18KX2)
+      continue;
+    RAM18KX2_cnt_total++;
+    if (trace_ >= 5) {
+      lprintf("\nRAM18KX2 instance #%u L=%u  dat_sz= %zu\n",
+        nd.id_, nd.lnum_, nd.realData_.size());
+      if (trace_ >= 6)
+        logVec(nd.realData_, " dat ");
+    }
+    for (const string& term : nd.realData_) {
+      if (term == "CLK_A1=$false") {
+        nd.disabledClocks_.emplace_back("CLK_A1");
+        continue;
+      }
+      if (term == "CLK_B1=$false") {
+        nd.disabledClocks_.emplace_back("CLK_B1");
+        continue;
+      }
+      if (term == "CLK_A2=$false") {
+        nd.disabledClocks_.emplace_back("CLK_A2");
+        continue;
+      }
+      if (term == "CLK_B2=$false") {
+        nd.disabledClocks_.emplace_back("CLK_B2");
+      }
+    }
+    if (not nd.disabledClocks_.empty())
+      RAM18KX2_cnt_disabled++;
+  }
+
+  if (trace_ >= 4) {
+    lprintf("DONE BLIF_file::createNodes()");
+    lprintf("   total #RAM18KX2 instances = %u", RAM18KX2_cnt_total);
+    if (RAM18KX2_cnt_total) {
+      lprintf("   #RAM18KX2 instances w disabled clocks = %u",
+              RAM18KX2_cnt_disabled);
+    }
+    flush_out(true);
+  }
+
   return true;
 }
 
@@ -2117,7 +2166,8 @@ bool BLIF_file::createPinGraph() noexcept {
       pr_get_inputs(par.ptype_, INP);
 
       const string& pinName = par.getInPin(pinIndex);
-      bool is_clock = pr_pin_is_clock(par.ptype_, pinName);
+      bool is_clock = pr_pin_is_clock(par.ptype_, pinName)
+                        and not par.isDisabledClock(pinName, *this);
 
       if (trace_ >= 5) {
         lprintf("      FabricParent par:  lnum_= %u  kw_= %s  ptype_= %s  pin[%u nm= %s%s]\n",
@@ -2218,6 +2268,12 @@ bool BLIF_file::createPinGraph() noexcept {
         assert(not inp.empty());
         if (not pr_pin_is_clock(cn.ptype_, inp))
           continue;
+        if (cn.isDisabledClock(inp, *this)) {
+          if (trace_ >= 6)
+            lprintf("    createPinGraph: skipping disabled clock-input-pin %s\n",
+                    inp.c_str());
+          continue;
+        }
 
         uint cn_realId = cn.realId(*this);
         key = hashCantor(cn_realId, i + 1) + max_key1;

planning/src/file_io/pln_blif_file.h

@@ -55,6 +55,9 @@ struct BLIF_file : public fio::MMapReader
     vector<string> inPins_;   // input pins from Prim-DB
     vector<string> inSigs_;   // input signals from blif-file
 
+    vector<string> disabledClocks_; // clock input pins of RAM18KX2 that are connected to $false
+                                    // and should not participate in pinGraph
+
     string out_;              // SOG output net (=signal) (real or virtual)
 
     uint virtualOrigin_ = 0;  // node-ID from which this virtual MOG is created
@@ -215,6 +218,20 @@ struct BLIF_file : public fio::MMapReader
 
     bool isDanglingTerm(uint term) const noexcept;
 
+    bool isDisabledClock(const string& pinName, const BLIF_file& bf) const noexcept {
+      assert(not pinName.empty());
+      if (pinName.empty())
+        return false;
+      if (ptype_ != prim::TDP_RAM18KX2)
+        return false;
+      const BNode* base = isVirtualMog() ? &bf.bnodeRef(virtualOrigin_) : this;
+      for (const string& x : base->disabledClocks_) {
+        if (x == pinName)
+          return true;
+      }
+      return false;
+    }
+
     struct CmpOut {
       bool operator()(const BNode* a, const BNode* b) const noexcept {
         return a->out_ < b->out_;

planning/src/main.cpp

@@ -1,4 +1,4 @@
-static const char* _pln_VERSION_STR = "pln0359";
+static const char* _pln_VERSION_STR = "pln0360";
 
 #include "RS/rsEnv.h"
 #include "util/pln_log.h"