Skip to content

Commit b40cf16

Browse files
serge-dsaserge-dsa
authored
Merge pull request #921 from os-fpga/checker_allow_port_feedthrough_EDA3235
clock checker: allow port feedthrough EDA-3235
2 parents 964124f + f5a27f8 commit b40cf16

File tree

5 files changed

+120
-56
lines changed

5 files changed

+120
-56
lines changed

‎planning/src/file_io/pln_blif_file.cpp‎

Lines changed: 84 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1199,12 +1199,6 @@ bool BLIF_file::createNodes() noexcept {
11991199
if (not starts_w_subckt(cs + 1, len - 1))
12001200
continue;
12011201
Fio::split_spa(lines_[L], V);
1202-
//if (L == 48) {
1203-
// string delWire1151 = "$delete_wire$1151";
1204-
// lputs8();
1205-
// int dTerm = findTermByNet(V, delWire1151);
1206-
// lprintf(" dTerm= %i\n", dTerm);
1207-
//}
12081202
if (V.size() > 1 and V.front() == ".subckt") {
12091203
Prim_t pt = pr_str2enum( V[1].c_str() );
12101204
if (pr_is_MOG(pt)) {
@@ -1997,7 +1991,35 @@ bool BLIF_file::checkClockSepar(vector<BNode*>& clocked) noexcept {
19971991
}
19981992
}
19991993

2000-
if (trace_ >= 6) {
1994+
// -- paint top-output nodes (and their incoming wires) Black
1995+
for (BNode* p : topOutputs_) {
1996+
const BNode& port = *p;
1997+
assert(!port.out_.empty());
1998+
assert(port.nw_id_);
1999+
if (!port.nw_id_)
2000+
continue;
2001+
NW::Node& nd = pg_.nodeRefCk(port.nw_id_);
2002+
nd.paintBlack();
2003+
uint par = port.parent_;
2004+
while (par) {
2005+
const BNode& parBn = bnodeRef(par);
2006+
assert(parBn.nw_id_);
2007+
if (!parBn.nw_id_)
2008+
break;
2009+
if (!parBn.is_WIRE())
2010+
break;
2011+
NW::Node& nwn = pg_.nodeRefCk(parBn.nw_id_);
2012+
nwn.paintBlack();
2013+
if (nwn.parent()) {
2014+
NW::Node& nwp = pg_.nodeRefCk(nwn.parent());
2015+
if (map_pg2blif(nwp.id_) == parBn.id_)
2016+
nwp.paintBlack();
2017+
}
2018+
par = parBn.parent_;
2019+
}
2020+
}
2021+
2022+
if (trace_ >= 5) {
20012023
lputs(" (Pin Graph) *** summary after B ***");
20022024
pg_.printSum(ls, 0);
20032025
lputs();
@@ -2025,13 +2047,16 @@ bool BLIF_file::checkClockSepar(vector<BNode*>& clocked) noexcept {
20252047
bool color_ok = true;
20262048
CStr viol_prefix = " [Error] clock-data separation ERROR";
20272049

2028-
// -- check that end-points of red edges are red
2050+
// -- check that end-points of red edges are red,
2051+
// the destination node may be black (output port)
20292052
for (NW::cEI E(pg_); E.valid(); ++E) {
20302053
const NW::Edge& ed = *E;
20312054
if (not ed.isRed())
20322055
continue;
20332056
NW::Node& p1 = pg_.nodeRef(ed.n1_);
20342057
NW::Node& p2 = pg_.nodeRef(ed.n2_);
2058+
if (p2.isBlack())
2059+
continue;
20352060
if (!p1.isRed() or !p2.isRed()) {
20362061
color_ok = false;
20372062
p1.markViol(true);
@@ -2170,50 +2195,57 @@ bool BLIF_file::createPinGraph() noexcept {
21702195

21712196
// -- link in-ports to out-ports via feedthrough wires
21722197
for (BNode* x : fabricRealNodes_) {
2173-
if (x->is_WIRE()) {
2174-
BNode& w = *x;
2175-
assert(w.data_.size() == 2);
2176-
const string& w_inp = w.data_.front();
2177-
const string& w_out = w.data_.back();
2178-
BNode* iport = findInputPort(w_inp);
2179-
if (!iport)
2180-
continue;
2181-
BNode* oport = findOutputPort(w_out);
2182-
if (!oport)
2183-
continue;
2184-
assert(iport->isTopInput());
2185-
assert(oport->isTopOutput());
2186-
// NW-nodes for i/o ports should exist already
2187-
assert(iport->nw_id_);
2188-
assert(oport->nw_id_);
2189-
assert(pg_.hasNode(iport->nw_id_));
2190-
assert(pg_.hasNode(oport->nw_id_));
2191-
assert(map_pg2blif(iport->nw_id_) == iport->id_);
2192-
assert(map_pg2blif(oport->nw_id_) == oport->id_);
2193-
2194-
// NW keys and nodes for wire pseudo-cell:
2195-
uint64_t w_k1 = hashCantor(w.id_, 1) + max_key1;
2196-
uint64_t w_k2 = hashCantor(w.id_, 2) + max_key1;
2197-
assert(w_k1);
2198-
assert(w_k2);
2199-
assert(w_k1 != w_k2);
2200-
uint w_n1 = pg_.insK(w_k1);
2201-
assert(w_n1);
2202-
uint w_n2 = pg_.insK(w_k2);
2203-
assert(w_n2);
2204-
pg2blif_.emplace(w_n1, w.id_);
2205-
pg2blif_.emplace(w_n2, w.id_);
2206-
pg_.setNodeName4(w_n1, w.id_, w.lnum_, 1, "FTwireI");
2207-
pg_.setNodeName4(w_n2, w.id_, w.lnum_, 2, "FTwireO");
2208-
2209-
// link feedthrough:
2210-
uint ee;
2211-
ee = pg_.linkNodes(iport->nw_id_, w_n1, false);
2212-
ee = pg_.linkNodes(w_n1, w_n2, true);
2213-
ee = pg_.linkNodes(w_n2, oport->nw_id_, false);
2214-
if (trace_ >= 11)
2215-
lprintf("\t\t ee = %u\n", ee);
2216-
}
2198+
BNode& w = *x;
2199+
if (not w.is_WIRE())
2200+
continue;
2201+
assert(w.data_.size() == 2);
2202+
const string& w_inp = w.data_.front();
2203+
const string& w_out = w.data_.back();
2204+
BNode* iport = findInputPort(w_inp);
2205+
if (!iport)
2206+
continue;
2207+
BNode* oport = findOutputPort(w_out);
2208+
if (!oport)
2209+
continue;
2210+
assert(iport->isTopInput());
2211+
assert(oport->isTopOutput());
2212+
// NW-nodes for i/o ports should exist already
2213+
assert(iport->nw_id_);
2214+
assert(oport->nw_id_);
2215+
assert(pg_.hasNode(iport->nw_id_));
2216+
assert(pg_.hasNode(oport->nw_id_));
2217+
assert(map_pg2blif(iport->nw_id_) == iport->id_);
2218+
assert(map_pg2blif(oport->nw_id_) == oport->id_);
2219+
2220+
// NW keys and nodes for wire pseudo-cell:
2221+
uint64_t w_k1 = hashCantor(w.id_, 1) + max_key1;
2222+
uint64_t w_k2 = hashCantor(w.id_, 2) + max_key1;
2223+
assert(w_k1);
2224+
assert(w_k2);
2225+
assert(w_k1 != w_k2);
2226+
uint w_n1 = pg_.insK(w_k1);
2227+
assert(w_n1);
2228+
uint w_n2 = pg_.insK(w_k2);
2229+
assert(w_n2);
2230+
pg2blif_.emplace(w_n1, w.id_);
2231+
pg2blif_.emplace(w_n2, w.id_);
2232+
w.nw_id_ = w_n2;
2233+
pg_.nodeRef(w_n1).markWire(true);
2234+
pg_.nodeRef(w_n2).markWire(true);
2235+
pg_.setNodeName4(w_n1, w.id_, w.lnum_, 1, "FTwireI");
2236+
pg_.setNodeName4(w_n2, w.id_, w.lnum_, 2, "FTwireO");
2237+
2238+
// make sure BNode::parent_ links are set
2239+
oport->parent_ = w.id_;
2240+
w.parent_ = iport->id_;
2241+
2242+
// link feedthrough:
2243+
uint ee;
2244+
ee = pg_.linkNodes(iport->nw_id_, w_n1, false);
2245+
ee = pg_.linkNodes(w_n1, w_n2, true);
2246+
ee = pg_.linkNodes(w_n2, oport->nw_id_, false);
2247+
if (trace_ >= 11)
2248+
lprintf("\t\t ee = %u\n", ee);
22172249
}
22182250

22192251
// -- link from input ports to fabric

‎planning/src/main.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
static const char* _pln_VERSION_STR = "pln0366";
1+
static const char* _pln_VERSION_STR = "pln0367";
22

33
#include "RS/rsEnv.h"
44
#include "RS/rsDeal.h"

‎planning/src/util/nw/Nw.cpp‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -318,6 +318,26 @@ uint NW::countRedNodes() const noexcept {
318318
return cnt;
319319
}
320320

321+
uint NW::countBlackNodes() const noexcept {
322+
uint cnt = 0;
323+
if (empty()) return 0;
324+
for (cNI I(*this); I.valid(); ++I) {
325+
if (I->isBlack())
326+
cnt++;
327+
}
328+
return cnt;
329+
}
330+
331+
uint NW::countWireNodes() const noexcept {
332+
uint cnt = 0;
333+
if (empty()) return 0;
334+
for (cNI I(*this); I.valid(); ++I) {
335+
if (I->wire_flag_)
336+
cnt++;
337+
}
338+
return cnt;
339+
}
340+
321341
bool NW::hasClockNodes() const noexcept {
322342
if (empty()) return false;
323343
for (cNI I(*this); I.valid(); ++I) {

‎planning/src/util/nw/Nw.h‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,8 @@ struct NW {
4444
static constexpr uint c_darkorchid4 = 13;
4545
static constexpr uint c_cyan = 14;
4646
static constexpr uint c_goldenrod3 = 15;
47-
static constexpr uint c_MAX_COLOR = 15;
47+
static constexpr uint c_Black = 16;
48+
static constexpr uint c_MAX_COLOR = 16;
4849

4950
struct Edge {
5051
uint id_ = 0;
@@ -64,6 +65,8 @@ struct NW {
6465
void paint(uint col) noexcept { color_ = col; }
6566
void paintRed() noexcept { color_ = c_Red; }
6667
bool isRed() const noexcept { return color_ == c_Red; }
68+
void paintBlack() noexcept { color_ = c_Black; }
69+
bool isBlack() const noexcept { return color_ == c_Black; }
6770

6871
bool valid() const noexcept { return n1_; }
6972
void inval() noexcept { ::memset(this, 0, sizeof(*this)); }
@@ -156,6 +159,7 @@ struct NW {
156159
void markOut(bool val) noexcept { out_flag_ = val; }
157160
void markClk(bool val) noexcept { clk_flag_ = val; }
158161
void markViol(bool val) noexcept { viol_flag_ = val; }
162+
void markWire(bool val) noexcept { wire_flag_ = val; }
159163
void markPrim(uint16_t pt) noexcept { prim_ = pt; }
160164

161165
bool isClk() const noexcept { return clk_flag_; }
@@ -170,6 +174,8 @@ struct NW {
170174
void paint(uint col) noexcept { color_ = col; }
171175
void paintRed() noexcept { color_ = c_Red; }
172176
bool isRed() const noexcept { return color_ == c_Red; }
177+
void paintBlack() noexcept { color_ = c_Black; }
178+
bool isBlack() const noexcept { return color_ == c_Black; }
173179

174180
// DATA:
175181
vecu edges_;
@@ -192,6 +198,7 @@ struct NW {
192198
bool out_flag_ = false;
193199
bool clk_flag_ = false;
194200
bool viol_flag_ = false;
201+
bool wire_flag_ = false;
195202
string name_;
196203
};
197204

@@ -280,6 +287,8 @@ struct NW {
280287
bool hasClockNodes() const noexcept;
281288
uint countClockNodes() const noexcept;
282289
uint countRedNodes() const noexcept;
290+
uint countBlackNodes() const noexcept;
291+
uint countWireNodes() const noexcept;
283292
uint countNamedNodes() const noexcept;
284293

285294
void getNodes(vecu& V) const noexcept { V = nids_; }

‎planning/src/util/nw/Nw_io.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -523,10 +523,13 @@ uint NW::printSum(ostream& os, uint16_t forDot) const noexcept {
523523
uint numNamedNodes = countNamedNodes();
524524
uint numRedNodes = countRedNodes();
525525
uint numRedEdges = countRedEdges();
526+
uint numBlackNodes = countBlackNodes();
527+
uint numWireNodes = countWireNodes();
526528

527529
dot_comment(os, forDot);
528-
os_printf(os, "#NamedNodes=%u #RedNodes= %u #RedEdges= %u\n",
529-
numNamedNodes, numRedNodes, numRedEdges);
530+
os_printf(os,
531+
"#NamedNodes=%u #RedN= %u #RedE= %u #BlackN= %u #WireN= %u\n",
532+
numNamedNodes, numRedNodes, numRedEdges, numBlackNodes, numWireNodes);
530533

531534
dot_comment(os, forDot);
532535
os_printf(os, "nr=(%u,%u) #Inp=%u #Out=%u\n",

0 commit comments

Comments
 (0)