Merge pull request #896 from os-fpga/checker_report_warnings_about_dangling

checker: report warnings about dangling RAM/DSP outputs

Author: serge-dsa

planning/src/RS/rsCheck.cpp

@@ -110,6 +110,13 @@ bool do_check_blif(CStr cfn,
   if (bfile.num_MOGs_ and tr >= 6) {
     ls << ">>>>> [NOTE] num_MOGs_ =  " << bfile.num_MOGs_ << endl;
   }
+  if (chk_ok) {
+    uint numWarn = bfile.numWarnings();
+    lprintf("=====    has warnings: %s", numWarn ? "YES" : "NO");
+    if (numWarn)
+      lprintf("  # WARNINGS= %u", numWarn);
+    lputs();
+  }
   lprintf("=====    passed: %s\n", chk_ok ? "YES" : "NO");
 
   flush_out(true);
@@ -122,8 +129,8 @@ bool do_check_blif(CStr cfn,
     return true;
   }
 
-  ls << "[Error] !!! BLIF is not OK !!!" << endl;
-  ls << "[Error] !!! " << bfile.err_msg_ << endl;
+  ls << "[Error]  ERROR  BLIF is not OK  ERROR" << endl;
+  ls << "[Error]  ERROR  " << bfile.err_msg_ << endl;
 
   flush_out(true);
   uint errLnum = std::max(bfile.err_lnum_, bfile.err_lnum2_);

planning/src/file_io/pln_blif_file.cpp

@@ -18,6 +18,8 @@ void BLIF_file::reset(CStr nm, uint16_t tr) noexcept {
   topOutputs_.clear();
   fabricNodes_.clear();
   fabricRealNodes_.clear();
+  dang_RAM_outputs_.clear();
+  dang_DSP_outputs_.clear();
   latches_.clear();
   constantNodes_.clear();
   rd_ok_ = chk_ok_ = false;
@@ -859,6 +861,12 @@ uint BLIF_file::countConstNodes() const noexcept {
   return cnt;
 }
 
+uint BLIF_file::numWarnings() const noexcept {
+  assert(dang_RAM_outputs_.size() < size_t(INT_MAX));
+  assert(dang_DSP_outputs_.size() < size_t(INT_MAX));
+  return dang_RAM_outputs_.size() + dang_DSP_outputs_.size();
+}
+
 uint BLIF_file::printCarryNodes(std::ostream& os) const noexcept {
   uint nn = numNodes();
   if (!nn) {
@@ -1087,6 +1095,8 @@ bool BLIF_file::createNodes() noexcept {
   topOutputs_.clear();
   fabricNodes_.clear();
   fabricRealNodes_.clear();
+  dang_RAM_outputs_.clear();
+  dang_DSP_outputs_.clear();
   latches_.clear();
   constantNodes_.clear();
   if (!rd_ok_) return false;
@@ -1702,11 +1712,16 @@ bool BLIF_file::linkNodes() noexcept {
     BNode* par = findFabricParent(nd.id_, nd.out_, pinIndex);
     if (!par) {
       if (nd.is_RAM() or nd.is_DSP()) {
+        bool is_ram = nd.is_RAM();
         // RAM or DSP output bits may be unused
-        if (trace_ >= 6) {
-          lprintf("skipping dangling cell output issue for %s\n",
-                  nd.is_RAM() ? "RAM" : "DSP" );
+        if (trace_ >= 5) {
+          lprintf("skipping dangling cell output issue for %s at line %u\n",
+                  is_ram ? "RAM" : "DSP", nd.lnum_);
         }
+        if (is_ram)
+          dang_RAM_outputs_.emplace_back(nd.id_);
+        else
+          dang_DSP_outputs_.emplace_back(nd.id_);
         continue;
       }
       err_msg_ = "dangling cell output: ";

planning/src/file_io/pln_blif_file.h

@@ -288,6 +288,8 @@ struct BLIF_file : public fio::MMapReader
   uint countWireNodes() const noexcept;
   uint countConstNodes() const noexcept;
 
+  uint numWarnings() const noexcept;
+
   uint printInputs(std::ostream& os, CStr spacer = nullptr) const noexcept;
   uint printOutputs(std::ostream& os, CStr spacer = nullptr) const noexcept;
   uint printNodes(std::ostream& os) const noexcept;
@@ -336,6 +338,9 @@ struct BLIF_file : public fio::MMapReader
   std::vector<BNode*> fabricNodes_, constantNodes_;
   std::vector<BNode*> fabricRealNodes_; // skip virtual SOGs
 
+  std::vector<uint> dang_RAM_outputs_;
+  std::vector<uint> dang_DSP_outputs_;
+
   std::vector<BNode*> latches_; // latches are not checked for now
 
   std::unordered_map<uint, uint> pg2blif_; // map IDs from NW to BLIF_file::BNode::id_

planning/src/main.cpp

@@ -1,4 +1,4 @@
-static const char* _pln_VERSION_STR = "pln0351";
+static const char* _pln_VERSION_STR = "pln0352";
 
 #include "RS/rsEnv.h"
 #include "util/pln_log.h"