build(deps): bump OpenFPGA from 7fff106 to 7c3de4c
#885
+1
−1
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Bumps OpenFPGA from
7fff106to7c3de4c.Commits
7c3de4cMerge pull request #1847 from lnis-uofu/bin_format9cb9394Merge pull request #1860 from lnis-uofu/patch_updatec8dd521Updated Patch Count65d6401Merge pull request #1858 from lnis-uofu/dependabot/submodules/vtr-verilog-to-...eabd445Merge pull request #1859 from lnis-uofu/dependabot/submodules/yosys-8893dadfc5c0f6modified testcases88e12a0modified test cases & xsd fileb3df515Bump yosys from408597bto8893daddd72461Bump vtr-verilog-to-routing from2eb6eb6to7569f734d8fae9seperate xml parser and bin parserDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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