diff --git a/CMakeLists.txt b/CMakeLists.txt index b1fe5715..dceb4f41 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -178,11 +178,11 @@ file(COPY ${PATCH_DIR}/base_fix/PATCHED/read_blif.cpp ${PATCH_DIR}/base_fix/PATCHED/read_circuit.cpp ${PATCH_DIR}/base_fix/PATCHED/read_circuit.h - #${PATCH_DIR}/base_fix/PATCHED/vpr_types.h - #${PATCH_DIR}/base_fix/PATCHED/vpr_context.h + ${PATCH_DIR}/base_fix/PATCHED/vpr_types.h + ${PATCH_DIR}/base_fix/PATCHED/vpr_context.h ${PATCH_DIR}/base_fix/PATCHED/read_options.cpp ${PATCH_DIR}/base_fix/PATCHED/read_options.h - #${PATCH_DIR}/base_fix/PATCHED/SetupVPR.cpp + ${PATCH_DIR}/base_fix/PATCHED/SetupVPR.cpp DESTINATION ${TARGET_DIR}) message(STATUS "NOTE: COPIED ${PATCH_DIR}/base_fix/PATCHED/read_.*\n to ${TARGET_DIR}/\n") @@ -275,13 +275,13 @@ file(COPY ${ENCRYPTION_CONFIG_PATH}/config.txt # ${OPENFPGA_DEST_DIR}/vtr-verilog-to-routing/libs/EXTERNAL/libtatum/libtatum/tatum #) -## Logical Levels -#FILE(COPY ${UTIL_SRC_DIR}/rsbe_utils.cpp -# ${UTIL_SRC_DIR}/rsbe_utils.h -# DESTINATION -# ${VPR_DEST_DIR}/src/util/ -#) -#message(STATUS "NOTE: ADDED to VPR src/util: rsbe_utils.cpp,h") +# Logical Levels +FILE(COPY ${UTIL_SRC_DIR}/rsbe_utils.cpp + ${UTIL_SRC_DIR}/rsbe_utils.h + DESTINATION + ${VPR_DEST_DIR}/src/util/ +) +message(STATUS "NOTE: ADDED to VPR src/util: rsbe_utils.cpp,h") # Logical Levels #FILE(COPY ${ANALYSIS_SRC_DIR}/timing_reports.cpp diff --git a/include/base_fix/PATCHED/SetupVPR.cpp b/include/base_fix/PATCHED/SetupVPR.cpp index 52235134..d4b3ce9a 100644 --- a/include/base_fix/PATCHED/SetupVPR.cpp +++ b/include/base_fix/PATCHED/SetupVPR.cpp @@ -87,86 +87,90 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile, * Does not do any error checking as this should have been done by * the various input checkers */ -void SetupVPR(const t_options* Options, - const bool TimingEnabled, +void SetupVPR(const t_options* options, + const bool timingenabled, const bool readArchFile, - t_file_name_opts* FileNameOpts, - t_arch* Arch, + t_file_name_opts* fileNameOpts, + t_arch* arch, t_model** user_models, t_model** library_models, - t_netlist_opts* NetlistOpts, - t_packer_opts* PackerOpts, - t_placer_opts* PlacerOpts, - t_annealing_sched* AnnealSched, - t_router_opts* RouterOpts, - t_analysis_opts* AnalysisOpts, - t_noc_opts* NocOpts, - t_server_opts* ServerOpts, - t_det_routing_arch* RoutingArch, - std::vector** PackerRRGraphs, - std::vector& Segments, - t_timing_inf* Timing, - bool* ShowGraphics, - int* GraphPause, - bool* SaveGraphics, - std::string* GraphicsCommands, - t_power_opts* PowerOpts, + t_netlist_opts* netlistOpts, + t_packer_opts* packerOpts, + t_placer_opts* placerOpts, + t_ap_opts* apOpts, + t_annealing_sched* annealSched, + t_router_opts* routerOpts, + t_analysis_opts* analysisOpts, + t_noc_opts* nocOpts, + t_server_opts* serverOpts, + t_det_routing_arch* routingArch, + std::vector** packerRRGraphs, + std::vector& segments, + t_timing_inf* timing, + bool* showGraphics, + int* graphPause, + bool* saveGraphics, + std::string* graphicsCommands, + t_power_opts* powerOpts, t_vpr_setup* vpr_setup) { using argparse::Provenance; auto& device_ctx = g_vpr_ctx.mutable_device(); - if (Options->CircuitName.value() == "") { + if (options->CircuitName.value() == "") { VPR_FATAL_ERROR(VPR_ERROR_BLIF_F, "No blif file found in arguments (did you specify an architecture file?)\n"); } - alloc_and_load_output_file_names(Options->CircuitName); - - //TODO: Move FileNameOpts setup into separate function - FileNameOpts->CircuitName = Options->CircuitName; - FileNameOpts->ArchFile = Options->ArchFile; - FileNameOpts->CircuitFile = Options->CircuitFile; - FileNameOpts->NetFile = Options->NetFile; - FileNameOpts->FlatPlaceFile = Options->FlatPlaceFile; - FileNameOpts->PlaceFile = Options->PlaceFile; - FileNameOpts->RouteFile = Options->RouteFile; - FileNameOpts->ActFile = Options->ActFile; - FileNameOpts->PowerFile = Options->PowerFile; - FileNameOpts->CmosTechFile = Options->CmosTechFile; - FileNameOpts->out_file_prefix = Options->out_file_prefix; - FileNameOpts->read_vpr_constraints_file = Options->read_vpr_constraints_file; - FileNameOpts->write_vpr_constraints_file = Options->write_vpr_constraints_file; - FileNameOpts->write_constraints_file = Options->write_constraints_file; - FileNameOpts->write_flat_place_file = Options->write_flat_place_file; - FileNameOpts->write_block_usage = Options->write_block_usage; - - FileNameOpts->verify_file_digests = Options->verify_file_digests; - - SetupNetlistOpts(*Options, *NetlistOpts); - SetupPlacerOpts(*Options, PlacerOpts); - SetupAnnealSched(*Options, AnnealSched); - SetupRouterOpts(*Options, RouterOpts); - SetupAnalysisOpts(*Options, *AnalysisOpts); - SetupPowerOpts(*Options, PowerOpts, Arch); - SetupNocOpts(*Options, NocOpts); - SetupServerOpts(*Options, ServerOpts); + alloc_and_load_output_file_names(options->CircuitName); + + //TODO: Move fileNameOpts setup into separate function + fileNameOpts->CircuitName = options->CircuitName; + fileNameOpts->ArchFile = options->ArchFile; + fileNameOpts->CircuitFile = options->CircuitFile; + fileNameOpts->NetFile = options->NetFile; + fileNameOpts->FlatPlaceFile = options->FlatPlaceFile; + fileNameOpts->PlaceFile = options->PlaceFile; + fileNameOpts->RouteFile = options->RouteFile; + fileNameOpts->ActFile = options->ActFile; + fileNameOpts->PowerFile = options->PowerFile; + fileNameOpts->CmosTechFile = options->CmosTechFile; + fileNameOpts->out_file_prefix = options->out_file_prefix; + fileNameOpts->read_vpr_constraints_file = options->read_vpr_constraints_file; + fileNameOpts->write_vpr_constraints_file = options->write_vpr_constraints_file; + fileNameOpts->write_constraints_file = options->write_constraints_file; + fileNameOpts->write_flat_place_file = options->write_flat_place_file; + fileNameOpts->write_block_usage = options->write_block_usage; + + fileNameOpts->verify_file_digests = options->verify_file_digests; + + SetupNetlistOpts(*options, *netlistOpts); + SetupPlacerOpts(*options, placerOpts); + SetupAnnealSched(*options, annealSched); + SetupRouterOpts(*options, routerOpts); + SetupAnalysisOpts(*options, *analysisOpts); + SetupPowerOpts(*options, powerOpts, arch); + SetupNocOpts(*options, nocOpts); + SetupServerOpts(*options, serverOpts); + + //save the device layout, which is required to parse the architecture file + arch->device_layout = options->device_layout; if (readArchFile == true) { vtr::ScopedStartFinishTimer t("Loading Architecture Description"); - switch (Options->arch_format) { + switch (options->arch_format) { case e_arch_format::VTR: - XmlReadArch(Options->ArchFile.value().c_str(), - TimingEnabled, - Arch, + XmlReadArch(options->ArchFile.value().c_str(), + timingenabled, + arch, device_ctx.physical_tile_types, device_ctx.logical_block_types); break; case e_arch_format::FPGAInterchange: VTR_LOG("Use FPGA Interchange device\n"); - FPGAInterchangeReadArch(Options->ArchFile.value().c_str(), - TimingEnabled, - Arch, + FPGAInterchangeReadArch(options->ArchFile.value().c_str(), + timingenabled, + arch, device_ctx.physical_tile_types, device_ctx.logical_block_types); break; @@ -176,8 +180,8 @@ void SetupVPR(const t_options* Options, } VTR_LOG("\n"); - *user_models = Arch->models; - *library_models = Arch->model_library; + *user_models = arch->models; + *library_models = arch->model_library; device_ctx.EMPTY_PHYSICAL_TILE_TYPE = nullptr; int num_inputs = 0; @@ -226,109 +230,119 @@ void SetupVPR(const t_options* Options, "Architecture contains no top-level block type containing '.output' models"); } - Segments = Arch->Segments; + segments = arch->Segments; - SetupSwitches(*Arch, RoutingArch, Arch->Switches, Arch->num_switches); - SetupRoutingArch(*Arch, RoutingArch); - SetupTiming(*Options, TimingEnabled, Timing); - SetupPackerOpts(*Options, PackerOpts); - RoutingArch->write_rr_graph_filename = Options->write_rr_graph_file; - RoutingArch->read_rr_graph_filename = Options->read_rr_graph_file; + SetupSwitches(*arch, routingArch, arch->Switches, arch->num_switches); + SetupRoutingArch(*arch, routingArch); + SetupTiming(*options, timingenabled, timing); + SetupPackerOpts(*options, packerOpts); + routingArch->write_rr_graph_filename = options->write_rr_graph_file; + routingArch->read_rr_graph_filename = options->read_rr_graph_file; - for (auto has_global_routing : Arch->layer_global_routing) { + for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); } //Setup the default flow, if no specific stages specified //do all - if (!Options->do_packing - && !Options->do_legalize - && !Options->do_placement - && !Options->do_routing - && !Options->do_analysis) { + if (!options->do_packing + && !options->do_legalize + && !options->do_placement + && !options->do_analytical_placement + && !options->do_routing + && !options->do_analysis) { //run all stages if none specified - PackerOpts->doPacking = STAGE_DO; - PlacerOpts->doPlacement = STAGE_DO; - RouterOpts->doRouting = STAGE_DO; - AnalysisOpts->doAnalysis = STAGE_AUTO; //Deferred until implementation status known + packerOpts->doPacking = STAGE_DO; + placerOpts->doPlacement = STAGE_DO; + apOpts->doAP = STAGE_SKIP; // AP not default. + routerOpts->doRouting = STAGE_DO; + analysisOpts->doAnalysis = STAGE_AUTO; //Deferred until implementation status known } else { //We run all stages up to the specified stage //Note that by checking in reverse order (i.e. analysis to packing) //we ensure that earlier stages override the default 'LOAD' action //set by later stages - if (Options->do_analysis) { - PackerOpts->doPacking = STAGE_LOAD; - PlacerOpts->doPlacement = STAGE_LOAD; - RouterOpts->doRouting = STAGE_LOAD; - AnalysisOpts->doAnalysis = STAGE_DO; + if (options->do_analysis) { + packerOpts->doPacking = STAGE_LOAD; + placerOpts->doPlacement = STAGE_LOAD; + routerOpts->doRouting = STAGE_LOAD; + analysisOpts->doAnalysis = STAGE_DO; } - if (Options->do_routing) { - PackerOpts->doPacking = STAGE_LOAD; - PlacerOpts->doPlacement = STAGE_LOAD; - RouterOpts->doRouting = STAGE_DO; - AnalysisOpts->doAnalysis = ((Options->do_analysis) ? STAGE_DO : STAGE_AUTO); //Always run analysis after routing + if (options->do_routing) { + packerOpts->doPacking = STAGE_LOAD; + placerOpts->doPlacement = STAGE_LOAD; + routerOpts->doRouting = STAGE_DO; + analysisOpts->doAnalysis = ((options->do_analysis) ? STAGE_DO : STAGE_AUTO); //Always run analysis after routing } - if (Options->do_placement) { - PackerOpts->doPacking = STAGE_LOAD; - PlacerOpts->doPlacement = STAGE_DO; + if (options->do_placement) { + packerOpts->doPacking = STAGE_LOAD; + placerOpts->doPlacement = STAGE_DO; } - if (Options->do_packing) { - PackerOpts->doPacking = STAGE_DO; + if (options->do_analytical_placement) { + // In the Analytical Placement flow, packing and placement are + // integrated. Thus, these stages are skipped. + packerOpts->doPacking = STAGE_SKIP; + placerOpts->doPlacement = STAGE_SKIP; + apOpts->doAP = STAGE_DO; } - if (Options->do_legalize) { - PackerOpts->doPacking = STAGE_LOAD; - PackerOpts->load_flat_placement = true; + if (options->do_packing) { + packerOpts->doPacking = STAGE_DO; + } + + if (options->do_legalize) { + packerOpts->doPacking = STAGE_LOAD; + packerOpts->load_flat_placement = true; } } ShowSetup(*vpr_setup); /* init global variables */ - vtr::out_file_prefix = Options->out_file_prefix; + vtr::out_file_prefix = options->out_file_prefix; /* Set seed for pseudo-random placement, default seed to 1 */ - vtr::srandom(PlacerOpts->seed); + vtr::srandom(placerOpts->seed); { vtr::ScopedStartFinishTimer t("Building complex block graph"); - alloc_and_load_all_pb_graphs(PowerOpts->do_power, RouterOpts->flat_routing); - *PackerRRGraphs = alloc_and_load_all_lb_type_rr_graph(); + alloc_and_load_all_pb_graphs(powerOpts->do_power, routerOpts->flat_routing); + *packerRRGraphs = alloc_and_load_all_lb_type_rr_graph(); } - if (RouterOpts->flat_routing) { + if (routerOpts->flat_routing) { vtr::ScopedStartFinishTimer timer("Allocate intra-cluster resources"); // The following two functions should be called when the data structured related to t_pb_graph_node, t_pb_type, // and t_pb_graph_edge are initialized - alloc_and_load_intra_cluster_resources(RouterOpts->has_choking_spot); + alloc_and_load_intra_cluster_resources(routerOpts->has_choking_spot); add_intra_tile_switches(); } - if ((Options->clock_modeling == ROUTED_CLOCK) || (Options->clock_modeling == DEDICATED_NETWORK)) { + if ((options->clock_modeling == ROUTED_CLOCK) || (options->clock_modeling == DEDICATED_NETWORK)) { ClockModeling::treat_clock_pins_as_non_globals(); } if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_LB_TYPE_RR_GRAPH)) { - echo_lb_type_rr_graphs(getEchoFileName(E_ECHO_LB_TYPE_RR_GRAPH), *PackerRRGraphs); + echo_lb_type_rr_graphs(getEchoFileName(E_ECHO_LB_TYPE_RR_GRAPH), *packerRRGraphs); } if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_PB_GRAPH)) { echo_pb_graph(getEchoFileName(E_ECHO_PB_GRAPH)); } - *GraphPause = Options->GraphPause; + *graphPause = options->GraphPause; - *ShowGraphics = Options->show_graphics; + *showGraphics = options->show_graphics; - *SaveGraphics = Options->save_graphics; - *GraphicsCommands = Options->graphics_commands; + *saveGraphics = options->save_graphics; + *graphicsCommands = options->graphics_commands; if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_ARCH)) { - EchoArch(getEchoFileName(E_ECHO_ARCH), device_ctx.physical_tile_types, device_ctx.logical_block_types, Arch); + EchoArch(getEchoFileName(E_ECHO_ARCH), device_ctx.physical_tile_types, device_ctx.logical_block_types, arch); } } @@ -423,6 +437,7 @@ static void SetupRoutingArch(const t_arch& Arch, /* Copy the tileable routing setting */ RoutingArch->tileable = Arch.tileable; + RoutingArch->perimeter_cb = Arch.perimeter_cb; RoutingArch->shrink_boundary = Arch.shrink_boundary; RoutingArch->through_channel = Arch.through_channel; RoutingArch->opin2all_sides = Arch.opin2all_sides; @@ -433,6 +448,7 @@ static void SetupRoutingArch(const t_arch& Arch, static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { RouterOpts->do_check_rr_graph = Options.check_rr_graph; RouterOpts->astar_fac = Options.astar_fac; + RouterOpts->astar_offset = Options.astar_offset; RouterOpts->router_profiler_astar_fac = Options.router_profiler_astar_fac; RouterOpts->bb_factor = Options.bb_factor; RouterOpts->criticality_exp = Options.criticality_exp; @@ -444,6 +460,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->pres_fac_mult = Options.pres_fac_mult; RouterOpts->max_pres_fac = Options.max_pres_fac; RouterOpts->route_type = Options.RouteType; + RouterOpts->route_verbosity = Options.route_verbosity; RouterOpts->full_stats = Options.full_stats; @@ -510,6 +527,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->generate_rr_node_overuse_report = Options.generate_rr_node_overuse_report; RouterOpts->flat_routing = Options.flat_routing; RouterOpts->has_choking_spot = Options.has_choking_spot; + RouterOpts->custom_3d_sb_fanin_fanout = Options.custom_3d_sb_fanin_fanout; RouterOpts->with_timing_analysis = Options.timing_analysis; } @@ -657,6 +675,8 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts) PlacerOpts->write_initial_place_file = Options.write_initial_place_file; + PlacerOpts->read_initial_place_file = Options.read_initial_place_file; + PlacerOpts->pad_loc_type = Options.pad_loc_type; PlacerOpts->place_chan_width = Options.PlaceChanWidth; diff --git a/include/base_fix/PATCHED/vpr_context.h b/include/base_fix/PATCHED/vpr_context.h index 5a6ad393..00a10aa7 100644 --- a/include/base_fix/PATCHED/vpr_context.h +++ b/include/base_fix/PATCHED/vpr_context.h @@ -5,10 +5,12 @@ #include #include +#include "prepack.h" #include "vpr_types.h" #include "vtr_ndmatrix.h" #include "vtr_optional.h" #include "vtr_vector.h" +#include "vtr_vector_map.h" #include "atom_netlist.h" #include "clustered_netlist.h" #include "rr_graph_view.h" @@ -33,6 +35,7 @@ #include "noc_traffic_flows.h" #include "noc_routing.h" #include "tatum/report/TimingPath.hpp" +#include "blk_loc_registry.h" #ifndef NO_SERVER @@ -73,34 +76,11 @@ struct AtomContext : public Context { /******************************************************************** * Atom Netlist ********************************************************************/ - /** - * @brief constructor - * - * In the constructor initialize the list of pack molecules to nullptr and defines a custom deletor for it - */ - AtomContext() - : list_of_pack_molecules(nullptr, free_pack_molecules) {} - - ///@brief Atom netlist + /// @brief Atom netlist AtomNetlist nlist; - ///@brief Mappings to/from the Atom Netlist to physically described .blif models + /// @brief Mappings to/from the Atom Netlist to physically described .blif models AtomLookup lookup; - - /** - * @brief The molecules associated with each atom block. - * - * This map is loaded in the pre-packing stage and freed at the very end of vpr flow run. - * The pointers in this multimap is shared with list_of_pack_molecules. - */ - std::multimap atom_molecules; - - /** - * @brief A linked list of all the packing molecules that are loaded in pre-packing stage. - * - * Is is useful in freeing the pack molecules at the destructor of the Atom context using free_pack_molecules. - */ - std::unique_ptr list_of_pack_molecules; }; /** @@ -159,7 +139,9 @@ struct DeviceContext : public Context { /** * @brief The device grid * - * This represents the physical layout of the device. To get the physical tile at each location (layer_num, x, y) the helper functions in this data structure should be used. + * This represents the physical layout of the device. + * To get the physical tile at each location (layer_num, x, y) the helper functions + * in this data structure should be used. */ DeviceGrid grid; /* @@ -309,69 +291,23 @@ struct ClusteringContext : public Context { * CLB Netlist ********************************************************************/ - ///@brief New netlist class derived from Netlist + /// @brief New netlist class derived from Netlist ClusteredNetlist clb_nlist; - /* Database for nets of each clb block pin after routing stage - * - post_routing_clb_pin_nets: - * mapping of pb_type pins to clustered net ids - * - pre_routing_net_pin_mapping: - * a copy of mapping for current pb_route index to previous pb_route index - * Record the previous pin mapping for finding the correct pin index during timing analysis - */ + /// @brief Database for nets of each clb block pin after routing stage. + /// - post_routing_clb_pin_nets: + /// mapping of pb_type pins to clustered net ids. + /// - pre_routing_net_pin_mapping: + /// a copy of mapping for current pb_route index to previous pb_route index + /// Record the previous pin mapping for finding the correct pin index during + /// timing analysis. std::map> post_routing_clb_pin_nets; std::map> pre_routing_net_pin_mapping; -}; - -/** - * @brief State relating to helper data structure using in the clustering stage - * - * This should contain helper data structures that are useful in the clustering/packing stage. - * They are encapsulated here as they are useful in clustering and reclustering algorithms that may be used - * in packing or placement stages. - */ -struct ClusteringHelperContext : public Context { - // A map used to save the number of used instances from each logical block type. - std::map num_used_type_instances; - - // Stats keeper for placement information during packing/clustering - t_cluster_placement_stats* cluster_placement_stats; - - // total number of models in the architecture - int num_models; - - int max_cluster_size; - t_pb_graph_node** primitives_list; - - bool enable_pin_feasibility_filter; - int feasible_block_array_size; - - // total number of CLBs - int total_clb_num; - - // A vector of routing resource nodes within each of logic cluster_ctx.blocks types [0 .. num_logical_block_type-1] - std::vector* lb_type_rr_graphs; - - // the utilization of external input/output pins during packing (between 0 and 1) - t_ext_pin_util_targets target_external_pin_util; - // During clustering, a block is related to un-clustered primitives with nets. - // This relation has three types: low fanout, high fanout, and transitive - // high_fanout_thresholds stores the threshold for nets to a block type to be considered high fanout - t_pack_high_fanout_thresholds high_fanout_thresholds; - - // A vector of unordered_sets of AtomBlockIds that are inside each clustered block [0 .. num_clustered_blocks-1] - // unordered_set for faster insertion/deletion during the iterative improvement process of packing + /// @brief A vector of unordered_sets of AtomBlockIds that are inside each + /// clustered block [0 .. num_clustered_blocks-1] + /// This is populated when the packing is loaded. vtr::vector> atoms_lookup; - - /** Stores the NoC group ID of each atom block. Atom blocks that belong - * to different NoC groups can't be clustered with each other into the - * same clustered block.*/ - vtr::vector atom_noc_grp_id; - - ~ClusteringHelperContext() { - delete[] primitives_list; - } }; /** @@ -391,14 +327,48 @@ struct PackingMultithreadingContext : public Context { * or related placer algorithm state. */ struct PlacementContext : public Context { - ///@brief Clustered block placement locations - vtr::vector_map block_locs; + private: + /** + * Determines if blk_loc_registry_ can be accessed by calling getter methods. + * This flag should be set to false at the beginning of the placement stage, + * and set to true at the end of placement. This ensures that variables that + * are subject to change during placement are kept local to the placement stage. + */ + bool loc_vars_are_accessible_ = true; + + /** + * @brief Stores block location information, which is subject to change during the + * placement stage. + */ + BlkLocRegistry blk_loc_registry_; + + public: - ///@brief Clustered pin placement mapping with physical pin - vtr::vector_map physical_pins; + const vtr::vector_map& block_locs() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.block_locs(); } + vtr::vector_map& mutable_block_locs() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_block_locs(); } + const GridBlock& grid_blocks() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.grid_blocks(); } + GridBlock& mutable_grid_blocks() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_grid_blocks(); } + vtr::vector_map& mutable_physical_pins() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.mutable_physical_pins(); } + const vtr::vector_map& physical_pins() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_.physical_pins(); } + BlkLocRegistry& mutable_blk_loc_registry() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_; } + const BlkLocRegistry& blk_loc_registry() const { VTR_ASSERT_SAFE(loc_vars_are_accessible_); return blk_loc_registry_; } - ///@brief Clustered block associated with each grid location (i.e. inverse of block_locs) - GridBlock grid_blocks; + /** + * @brief Makes blk_loc_registry_ inaccessible through the getter methods. + * + * This method should be called at the beginning of the placement stage to + * guarantee that the placement stage code does not access block location variables + * stored in the global state. + */ + void lock_loc_vars() { VTR_ASSERT_SAFE(loc_vars_are_accessible_); loc_vars_are_accessible_ = false; } + + /** + * @brief Makes blk_loc_registry_ accessible through the getter methods. + * + * This method should be called at the end of the placement stage to + * make the block location information accessible for subsequent stages. + */ + void unlock_loc_vars() { VTR_ASSERT_SAFE(!loc_vars_are_accessible_); loc_vars_are_accessible_ = true; } ///@brief The pl_macros array stores all the placement macros (usually carry chains). std::vector pl_macros; @@ -537,15 +507,24 @@ struct FloorplanningContext : public Context { /** * @brief Floorplanning constraints in the compressed grid coordinate system. * + * Indexing --> [0..grid.num_layers-1][0..numClusters-1] + * * Each clustered block has a logical type with a corresponding compressed grid. * Compressed floorplanning constraints are calculated by translating the grid locations * of floorplanning regions to compressed grid locations. To ensure regions do not enlarge: * - The bottom left corner is rounded up to the nearest compressed location. * - The top right corner is rounded down to the nearest compressed location. + * + * When the floorplanning constraint spans across multiple layers, a compressed + * constraints is created for each a layer that the original constraint includes. + * This is because blocks of the same type might have different (x, y) locations + * in different layers, and as result, their compressed locations in each layer + * may correspond to a different physical (x, y) location. + * */ - vtr::vector compressed_cluster_constraints; + std::vector> compressed_cluster_constraints; - std::vector overfull_regions; + std::vector overfull_partition_regions; }; /** @@ -571,7 +550,8 @@ struct NocContext : public Context { /** * @brief Stores all the communication happening between routers in the NoC * - * Contains all of the traffic flows that describe which pairs of logical routers are communicating and also some metrics and constraints on the data transfer between the two routers. + * Contains all of the traffic flows that describe which pairs of logical routers are + * communicating and also some metrics and constraints on the data transfer between the two routers. * * * This is created from a user supplied .flows file. @@ -708,9 +688,6 @@ class VprContext : public Context { const ClusteringContext& clustering() const { return clustering_; } ClusteringContext& mutable_clustering() { return clustering_; } - const ClusteringHelperContext& cl_helper() const { return helper_; } - ClusteringHelperContext& mutable_cl_helper() { return helper_; } - const PlacementContext& placement() const { return placement_; } PlacementContext& mutable_placement() { return placement_; } @@ -743,8 +720,6 @@ class VprContext : public Context { PowerContext power_; ClusteringContext clustering_; - ClusteringHelperContext helper_; - PlacementContext placement_; RoutingContext routing_; FloorplanningContext constraints_; diff --git a/include/base_fix/PATCHED/vpr_types.h b/include/base_fix/PATCHED/vpr_types.h index d6c961c3..28282924 100644 --- a/include/base_fix/PATCHED/vpr_types.h +++ b/include/base_fix/PATCHED/vpr_types.h @@ -48,6 +48,7 @@ #include "rr_graph_fwd.h" #include "rr_graph_cost.h" #include "rr_graph_type.h" +#include "vtr_vector_map.h" /******************************************************************************* * Global data types and constants @@ -94,12 +95,6 @@ enum class ScreenUpdatePriority { /* Used to avoid floating-point errors when comparing values close to 0 */ #define EPSILON 1.e-15 -#define FIRST_ITER_WIRELENTH_LIMIT 0.85 /* If used wirelength exceeds this value in first iteration of routing, do not route */ - -/* Defining macros for the placement_ctx t_grid_blocks. Assumes that ClusterBlockId's won't exceed positive 32-bit integers */ -constexpr auto EMPTY_BLOCK_ID = ClusterBlockId(-1); -constexpr auto INVALID_BLOCK_ID = ClusterBlockId(-2); - /* * Files */ @@ -115,12 +110,18 @@ constexpr auto INVALID_BLOCK_ID = ClusterBlockId(-2); # define UNDEFINED (-1) #endif +///@brief Router lookahead types. enum class e_router_lookahead { - CLASSIC, ///> valid_primitives; - - public: - // Moves primitives that are inflight to the tried map - void move_inflight_to_tried(); - - /** - * @brief Move the primitive at (it) to inflight and increment the current iterator. - * - * Because the element at (it) is deleted from valid_primitives, (it) is incremented to keep it valid and pointing at the next element. - * - * @param pb_type_index: is the index of this pb_type in valid_primitives vector - * @param it: is the iterator pointing at the element that needs to be moved to inflight - */ - void move_primitive_to_inflight(int pb_type_index, std::unordered_multimap::iterator& it); - - /** - * @brief Move the primitive at (it) to invalid and increment the current iterator - * - * Because the element at (it) is deleted from valid_primitives, (it) is incremented to keep it valid and pointing at the next element. - * - * @param pb_type_index: is the index of this pb_type in valid_primitives vector - * @param it: is the iterator pointing at the element that needs to be moved to invalid - */ - void invalidate_primitive_and_increment_iterator(int pb_type_index, std::unordered_multimap::iterator& it); - - /** - * @brief Add a primitive in its correct location in valid_primitives vector based on its pb_type - * - * @param cluster_placement_primitive: a pair of the cluster_placement_primtive and its corresponding index(for reference in pb_graph_node) - */ - void insert_primitive_in_valid_primitives(std::pair cluster_placement_primitive); - - /** - * @brief Move all the primitives from (in_flight and tried) maps to valid primitives and clear (in_flight and tried) - */ - void flush_intermediate_queues(); - - /** - * @brief Move all the primitives from invalid to valid_primitives and clear the invalid map - */ - void flush_invalid_queue(); - - /** - * @brief Return true if the in_flight map is empty (no primitive is in_flight currently) - */ - bool in_flight_empty(); - - /** - * @brief Return the type of the first element of the primitives currently being considered - */ - t_pb_type* in_flight_type(); - - /** - * @brief free the dynamically allocated memory for primitives - */ - void free_primitives(); - - private: - std::unordered_multimap in_flight; /// tried; /// invalid; ///& queue); -}; - /****************************************************************** * Timing data types *******************************************************************/ @@ -627,6 +535,7 @@ struct t_2D_bb { VTR_ASSERT(ymax_ >= ymin_); VTR_ASSERT(layer_num_ >= 0); } + int xmin = OPEN; int xmax = OPEN; int ymin = OPEN; @@ -833,73 +742,6 @@ struct t_block_loc { bool is_fixed = false; }; -///@brief Stores the clustered blocks placed at a particular grid location -struct t_grid_blocks { - int usage; ///capacity] - */ - std::vector blocks; - - /** - * @brief Test if a subtile at a grid location is occupied by a block. - * - * Returns true if the subtile corresponds to the passed-in id is not - * occupied by a block at this grid location. The subtile id serves - * as the z-dimensional offset in the grid indexing. - */ - inline bool subtile_empty(size_t isubtile) const { - return blocks[isubtile] == EMPTY_BLOCK_ID; - } -}; - -class GridBlock { - public: - GridBlock() = default; - - GridBlock(size_t width, size_t height, size_t layers) { - grid_blocks_.resize({layers, width, height}); - } - - inline void initialized_grid_block_at_location(const t_physical_tile_loc& loc, int num_sub_tiles) { - grid_blocks_[loc.layer_num][loc.x][loc.y].blocks.resize(num_sub_tiles, EMPTY_BLOCK_ID); - } - - inline void set_block_at_location(const t_pl_loc& loc, ClusterBlockId blk_id) { - grid_blocks_[loc.layer][loc.x][loc.y].blocks[loc.sub_tile] = blk_id; - } - - inline ClusterBlockId block_at_location(const t_pl_loc& loc) const { - return grid_blocks_[loc.layer][loc.x][loc.y].blocks[loc.sub_tile]; - } - - inline size_t num_blocks_at_location(const t_physical_tile_loc& loc) const { - return grid_blocks_[loc.layer_num][loc.x][loc.y].blocks.size(); - } - - inline int set_usage(const t_physical_tile_loc loc, int usage) { - return grid_blocks_[loc.layer_num][loc.x][loc.y].usage = usage; - } - - inline int get_usage(const t_physical_tile_loc loc) const { - return grid_blocks_[loc.layer_num][loc.x][loc.y].usage; - } - - inline bool is_sub_tile_empty(const t_physical_tile_loc loc, int sub_tile) const { - return grid_blocks_[loc.layer_num][loc.x][loc.y].subtile_empty(sub_tile); - } - - inline void clear() { - grid_blocks_.clear(); - } - - private: - vtr::NdMatrix grid_blocks_; -}; - ///@brief Names of various files struct t_file_name_opts { std::string ArchFile; @@ -1102,7 +944,7 @@ class t_place_algorithm { e_place_algorithm algo = e_place_algorithm::CRITICALITY_TIMING_PLACE; }; -enum e_pad_loc_type { +enum class e_pad_loc_type { FREE, RANDOM }; @@ -1235,6 +1077,7 @@ struct t_placer_opts { enum e_pad_loc_type pad_loc_type; std::string constraints_file; std::string write_initial_place_file; + std::string read_initial_place_file; enum pfreq place_freq; int recompute_crit_iter; int inner_loop_recompute_divider; @@ -1307,6 +1150,26 @@ struct t_placer_opts { bool enable_cascade_placer = false; }; + +/****************************************************************** + * Analytical Placer data types + *******************************************************************/ + +/** + * @brief Various options for the Analytical Placer. + * + * @param doAnalyticalPlacement + * True if analytical placement is supposed to be done in the CAD + * flow. False if otherwise. + */ +struct t_ap_opts { + e_stage_action doAP; +}; + +/****************************************************************** + * Router data types + *******************************************************************/ + /* All the parameters controlling the router's operation are in this * * structure. * * first_iter_pres_fac: Present sharing penalty factor used for the * @@ -1344,6 +1207,8 @@ struct t_placer_opts { * an essentially breadth-first search, astar_fac = 1 is near * * the usual astar algorithm and astar_fac > 1 are more * * aggressive. * + * astar_offset: Offset that is subtracted from the lookahead (expected * + * future costs) in the timing-driven router. * * max_criticality: The maximum criticality factor (from 0 to 1) any sink * * will ever have (i.e. clip criticality to this number). * * criticality_exp: Set criticality to (path_length(sink) / longest_path) ^ * @@ -1434,6 +1299,7 @@ struct t_router_opts { enum e_router_algorithm router_algorithm; enum e_base_cost_type base_cost_type; float astar_fac; + float astar_offset; float router_profiler_astar_fac; float max_criticality; float criticality_exp; @@ -1458,6 +1324,7 @@ struct t_router_opts { int router_debug_iteration; e_router_lookahead lookahead_type; int max_convergence_count; + int route_verbosity; float reconvergence_cpd_threshold; e_router_initial_timing initial_timing; bool update_lower_bound_delays; @@ -1483,6 +1350,8 @@ struct t_router_opts { bool flat_routing; bool has_choking_spot; + int custom_3d_sb_fanin_fanout = 1; + bool with_timing_analysis; // Options related to rr_node reordering, for testing and possible cache optimization @@ -1511,22 +1380,22 @@ struct t_analysis_opts { // used to store NoC specific options, when supplied as an input by the user struct t_noc_opts { - bool noc; ///>> t_clb_op typedef std::vector> t_arch_switch_fanin; -/** - * @brief Free the linked list that saves all the packing molecules. - */ -void free_pack_molecules(t_pack_molecule* list_of_pack_molecules); - -/** - * @brief Free the linked lists to placement locations based on status of primitive inside placement stats data structure. - */ -void free_cluster_placement_stats(t_cluster_placement_stats* cluster_placement_stats); +struct pair_hash { + std::size_t operator()(const std::pair& p) const noexcept { + return std::hash()(p.first) ^ (std::hash()(p.second) << 1); + } +}; #endif diff --git a/include/util_fix/rsbe_utils.cpp b/include/util_fix/rsbe_utils.cpp index 78fd1fbf..f7e806b6 100644 --- a/include/util_fix/rsbe_utils.cpp +++ b/include/util_fix/rsbe_utils.cpp @@ -20,7 +20,6 @@ #include "pack_types.h" #include "device_grid.h" #include "timing_fail_error.h" -#include "re_cluster_util.h" namespace rsbe {