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revert OpenFPGA to Oct10 2de9864eeb8 #905

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Merged
merged 2 commits into from
Oct 24, 2024
Merged

revert OpenFPGA to Oct10 2de9864eeb8 #905

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81c2726
revert OpenFPGA to Oct10 2de9864eeb8
serge-rs Oct 24, 2024
bbfc21f
undo patch-set changes for reverting OpenFPGA to 2de9864eeb8
serge-rs Oct 24, 2024
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58 changes: 18 additions & 40 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -130,30 +130,25 @@ FILE(COPY ${EBLIF_TRANSFORM_SRC_H}
DESTINATION
${EBLIF_TRANSFORM_DEST})

message(STATUS "NOTE: PATCHING VPR pack/pb_pin_fixup\n")
FILE(COPY ${PACKER_SRC_DIR}/post_routing_pb_pin_fixup.cpp
# patch VPR
FILE(COPY ${PACKER_SRC_DIR}/cluster.cpp
${PACKER_SRC_DIR}/cluster_util.cpp
${PACKER_SRC_DIR}/cluster_util.h
${PACKER_SRC_DIR}/output_clustering.cpp
${PACKER_SRC_DIR}/output_clustering.h
${PACKER_SRC_DIR}/cluster_router.cpp
${PACKER_SRC_DIR}/post_routing_pb_pin_fixup.cpp
DESTINATION
${VPR_DEST_DIR}/src/pack)

# patch VPR
#FILE(COPY ${PACKER_SRC_DIR}/cluster.cpp
# ${PACKER_SRC_DIR}/cluster_util.cpp
# ${PACKER_SRC_DIR}/cluster_util.h
# ${PACKER_SRC_DIR}/output_clustering.cpp
# ${PACKER_SRC_DIR}/output_clustering.h
# ${PACKER_SRC_DIR}/cluster_router.cpp
# ${PACKER_SRC_DIR}/post_routing_pb_pin_fixup.cpp
# DESTINATION
# ${VPR_DEST_DIR}/src/pack)

# add to VPR/pack
#FILE(COPY ${PACKER_SRC_DIR}/nl_Par.h
# ${PACKER_SRC_DIR}/nl_Par.cpp
# ${PACKER_SRC_DIR}/pinc_log.h
# ${PACKER_SRC_DIR}/pinc_log.cpp
# DESTINATION
# ${VPR_DEST_DIR}/src/pack)
#message(STATUS "NOTE: ADDED to VPR src/pack: nl_Par.cpp,h pinc_log.cpp,h")
FILE(COPY ${PACKER_SRC_DIR}/nl_Par.h
${PACKER_SRC_DIR}/nl_Par.cpp
${PACKER_SRC_DIR}/pinc_log.h
${PACKER_SRC_DIR}/pinc_log.cpp
DESTINATION
${VPR_DEST_DIR}/src/pack)
message(STATUS "NOTE: ADDED to VPR src/pack: nl_Par.cpp,h pinc_log.cpp,h")

# add to VPR/base
file(COPY
Expand All @@ -174,7 +169,7 @@ message(STATUS "NOTE: OVERWRITING netlist_writer.cpp")
file(COPY ${PATCH_DIR}/base_fix/PATCHED/netlist_writer.cpp DESTINATION ${TARGET_DIR})
message(STATUS "NOTE: COPIED ${PATCH_DIR}/base_fix/PATCHED/netlist_writer.cpp\n to ${TARGET_DIR}/\n")

#message(STATUS "NOTE: PATCHING base/vpr_api.cpp ..")
message(STATUS "NOTE: PATCHING-COPYING base/vpr_api.cpp ..")
#set(DIFF_FILE ${PATCH_DIR}/base_fix/DIFF/vpr_api_cpp.diff)
#apply_patch(${DIFF_FILE} ${TARGET_DIR} "base/vpr_api.cpp")

Expand Down Expand Up @@ -213,26 +208,9 @@ set(DIFF_FILE ${PATCH_DIR}/libpugiutil_fix/DIFF/pugixml_util_cpp.diff)
apply_patch(${DIFF_FILE} ${CMAKE_CURRENT_SOURCE_DIR}/OpenFPGA/vtr-verilog-to-routing/libs/libpugiutil/src "pugixml_util.cpp")

# copy RS additions and patch CMakefiles
message(STATUS "NOTE: COPYING/PATCHING OpenFPGA CMakefiles..")
message(STATUS "NOTE: COPYING OpenFPGA CMakefile..")
#set(DIFF_FILE ${PATCH_DIR}/CMAKE_fix/OpenFPGA_CMake.diff)
#apply_patch(${DIFF_FILE} ${CMAKE_CURRENT_SOURCE_DIR}/OpenFPGA "OpenFPGA CMakefile")
set(DIFF_FILE ${PATCH_DIR}/CMAKE_fix/PATCHED_OpenFPGA/libs_cmakefile.diff)
apply_patch(${DIFF_FILE} ${CMAKE_CURRENT_SOURCE_DIR}/OpenFPGA/libs "OpenFPGA/libs CMakefile")

set(DIFF_FILE ${PATCH_DIR}/CMAKE_fix/PATCHED_OpenFPGA/openfpga_src_CMakefile.diff)
apply_patch(${DIFF_FILE} ${CMAKE_CURRENT_SOURCE_DIR}/OpenFPGA/openfpga "OpenFPGA/openfpga CMakefile")

file(COPY
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx.capnp
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx.capnp.c++
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx.capnp.h
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx_capnp.h
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx_capnp_impl.h
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx.cpp
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx.h
${PATCH_DIR}/openfpga/annotation/unique_blocks_uxsdcxx_interface.h
DESTINATION
${CMAKE_CURRENT_SOURCE_DIR}/OpenFPGA/openfpga/src/annotation)

# temporarily swithed to copying because of "partial patch" issue in Raptor build.
file(COPY
Expand Down Expand Up @@ -298,7 +276,7 @@ FILE(COPY ${TATUM_SRC_DIR}/TimingReporter.hpp
${OPENFPGA_DEST_DIR}/vtr-verilog-to-routing/libs/EXTERNAL/libtatum/libtatum/tatum
)

# Logical Levels
## Logical Levels
FILE(COPY ${UTIL_SRC_DIR}/rsbe_utils.cpp
${UTIL_SRC_DIR}/rsbe_utils.h
DESTINATION
Expand Down
2 changes: 1 addition & 1 deletion OpenFPGA
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Submodule OpenFPGA updated 127 files
45 changes: 16 additions & 29 deletions include/CMAKE_fix/PATCHED_VPR/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -99,26 +99,15 @@ add_library(libvpr STATIC
target_include_directories(libvpr PUBLIC ${LIB_INCLUDE_DIRS})
target_include_directories(libvpr PUBLIC ${READ_EDIF_SRC_DIR})

# Find if Eigen is installed. Eigen is used within the Analytical Solver of the
# Analytical Placement flow. If Eigen is not installed, certain solvers cannot
# be used.
find_package(Eigen3 3.3 NO_MODULE)
if (TARGET Eigen3::Eigen)
target_link_libraries (libvpr Eigen3::Eigen)
target_compile_definitions(libvpr PUBLIC -DEIGEN_INSTALLED)
message(STATUS "Eigen3: Found")
else ()
message(STATUS "Eigen3: Not Found. Some features may be disabled.")
endif (TARGET Eigen3::Eigen)

#VPR_ANALYTIC_PLACE is initialized in the root CMakeLists
# NOTE: This is the cluster-level Analytical Placement which existed before the
# flat Analytical Placement flow.
#Check Eigen dependency
if(${VPR_ANALYTIC_PLACE})
message(STATUS "VPR Analytic Placement: Requested")
find_package(Eigen3 3.3 NO_MODULE)
if (TARGET Eigen3::Eigen)
message(STATUS "VPR Analytic Placement dependency (Eigen3): Found")
message(STATUS "VPR Analytic Placement: Enabled")
target_link_libraries (libvpr Eigen3::Eigen)
target_compile_definitions(libvpr PUBLIC -DENABLE_ANALYTIC_PLACE)
else ()
message(STATUS "VPR Analytic Placement dependency (Eigen3): Not Found (Download manually with sudo apt install libeigen3-dev, and rebuild)")
Expand All @@ -143,21 +132,19 @@ endif ()
set_target_properties(libvpr PROPERTIES PREFIX "") #Avoid extra 'lib' prefix

#Specify link-time dependencies
find_package(ZLIB)
target_link_libraries(libvpr
libvtrutil
libarchfpga
libsdcparse
libblifparse
libtatum
libargparse
libpugixml
librrgraph
libreadedif
${OPENSSL_LIBRARIES}
${VERIFIC_LIBS}
ZLIB::ZLIB dl
)
libvtrutil
libarchfpga
libsdcparse
libblifparse
libtatum
libargparse
libpugixml
librrgraph
libreadedif
${OPENSSL_LIBRARIES}
${VERIFIC_LIBS} dl
)

if(VPR_USE_SERVER)
target_link_libraries(libvpr
Expand Down Expand Up @@ -343,7 +330,7 @@ file(GLOB_RECURSE TEST_SOURCES test/*.cpp)
add_executable(test_vpr ${TEST_SOURCES})
target_link_libraries(test_vpr
Catch2::Catch2WithMain
libvpr -lz)
libvpr)

#Suppress IPO link warnings if IPO is enabled
get_target_property(TEST_VPR_USES_IPO vpr INTERPROCEDURAL_OPTIMIZATION)
Expand Down
18 changes: 4 additions & 14 deletions include/analysis_fix/timing_reports.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12,18 +12,13 @@

#include "VprTimingGraphResolver.h"

void generate_setup_timing_stats(const std::string& prefix,
const SetupTimingInfo& timing_info,
const AnalysisDelayCalculator& delay_calc,
const t_analysis_opts& analysis_opts,
bool is_flat,
const BlkLocRegistry& blk_loc_registry) {
void generate_setup_timing_stats(const std::string& prefix, const SetupTimingInfo& timing_info, const AnalysisDelayCalculator& delay_calc, const t_analysis_opts& analysis_opts, bool is_flat) {
auto& timing_ctx = g_vpr_ctx.timing();
auto& atom_ctx = g_vpr_ctx.atom();

print_setup_timing_summary(*timing_ctx.constraints, *timing_info.setup_analyzer(), "Final ", analysis_opts.write_timing_summary);

VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry);
VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat);
resolver.set_detail_level(analysis_opts.timing_report_detail);

tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints);
Expand All @@ -37,18 +32,13 @@ void generate_setup_timing_stats(const std::string& prefix,
timing_reporter.report_unconstrained_setup(prefix + "report_unconstrained_timing.setup.rpt", *timing_info.setup_analyzer());
}

void generate_hold_timing_stats(const std::string& prefix,
const HoldTimingInfo& timing_info,
const AnalysisDelayCalculator& delay_calc,
const t_analysis_opts& analysis_opts,
bool is_flat,
const BlkLocRegistry& blk_loc_registry) {
void generate_hold_timing_stats(const std::string& prefix, const HoldTimingInfo& timing_info, const AnalysisDelayCalculator& delay_calc, const t_analysis_opts& analysis_opts, bool is_flat) {
auto& timing_ctx = g_vpr_ctx.timing();
auto& atom_ctx = g_vpr_ctx.atom();

print_hold_timing_summary(*timing_ctx.constraints, *timing_info.hold_analyzer(), "Final ");

VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat, blk_loc_registry);
VprTimingGraphResolver resolver(atom_ctx.nlist, atom_ctx.lookup, *timing_ctx.graph, delay_calc, is_flat);
resolver.set_detail_level(analysis_opts.timing_report_detail);

tatum::TimingReporter timing_reporter(resolver, *timing_ctx.graph, *timing_ctx.constraints);
Expand Down
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