MIPI_TX spec updated

Author: moinijaz

specs_internal/MIPI_TX.yaml

@@ -0,0 +1,134 @@
+# Periphery Primitives Parameters and Properties (P4)
+#
+# This file contains the list of Verilog parameters and SDC properties that are
+# allowed for periphery primitives.
+#
+# See https://rapidsilicon.atlassian.net/wiki/spaces/RS/pages/214368265/Periphery+Primitive+Parameters+and+Properties+Definitions+P4DEF for more details
+#
+# The name needs to match the filename root
+# name: <primitive name>
+# desc: <optional description>
+#
+# ports:
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#   <portname>:
+#       dir: <input, output, inout>
+#       desc: <optional description>
+#
+# # set as Verilog parameter
+# parameters:
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>
+#    <parameter_name>:
+#        desc: <description>
+#        values:
+#          - <enum_name>
+#          - <enum_name>  
+#
+# # set in SDC or by synthesis attribute
+# properties:
+#    <property_name>:
+#        desc: <description>
+#        values: 
+#          - <enum_name>
+#          - <enum_name>
+#    <property_name>:
+#        desc: <description>
+#          - <enum_name>
+#          - <enum_name>
+#
+# primitive name should match the filename root.
+name: MIPI_TX
+desc: MIPI Transmitter
+category: periphery
+
+ports:
+   RST:
+     dir: input
+     desc: Active-low, asynchronous reset
+   RX_CLK:
+     dir: input
+     desc: MIPI RX_IO clock input, PLL_CLK
+   PLL_LOCK:
+     dir: input
+     desc: PLL lock input
+   CLK_IN: 
+     dir: input
+     desc: Fabric core clock input
+     bb_attributes: clkbuf_sink
+   HS_TX_DATA[WIDTH-1:0]:
+     dir: input
+     desc: Parallel Data input bus from fabric
+   HS_TXD_VALID:
+     dir: input
+     desc: Load word input from Fabric
+   HS_EN:
+     dir: input
+     desc: EN HS Data Transmission (From Fabric)
+   TX_LP_DP:
+     dir: input
+     desc: LP TX Data positive from the Fabric
+   TX_LP_DN:
+     dir: input
+     desc: LP TX Data negative from the Fabric
+   LP_EN:
+     dir: input
+     desc: EN LP Data Transmission (From Fabric). Active high signal. This is a common signal between MIPI RX/TX interface.
+   TX_ODT_EN:
+     dir: input
+     desc: EN Termination
+   DLY_LOAD:
+     dir: input
+     desc: Delay load input, from Fabric 
+   DLY_ADJ:
+     dir: input
+     desc: Delay adjust input, from Fabric
+   DLY_INCDEC:
+     dir: input
+     desc: Delay increment / decrement input, from Fabric
+   TX_OE:
+     dir: output
+     desc: IBUF OE signal for MIPI O_BUF
+   TX_DP:
+     dir: output
+     desc: Serial Data output to O_BUF
+   TX_DN:
+     dir: output
+     desc: Serial Data output to O_BUF
+   CHANNEL_BOND_SYNC_IN:
+     dir: input
+     desc: Channel bond sync input
+   CHANNEL_BOND_SYNC_OUT:
+     dir: output
+     desc: Channel bond sync output
+
+# set as Verilog parameter in netlist    
+parameters:
+    WIDTH:
+      desc: Width of input data to serializer (3-10)
+      type: integer
+      default: 4
+      range: 3 .. 10
+    EN_ODLY:
+      desc: True or False
+      default: "FALSE"
+      values:
+        - "TRUE"
+        - "FALSE"
+    LANE_MODE:
+      desc: Master or Slave
+      default: "Master"
+      values:
+        - "Master"
+        - "Slave"
+    DELAY:
+      desc: Fixed TAP delay value (0-63)
+      type: integer
+      default: 0
+      range: 0 .. 63
+