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Merge pull request #131 from os-fpga/fail_sim_1.5.7
Fail sim 1.5.7
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‎blackbox_models/cell_sim_blackbox.v‎

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@@ -118,6 +118,42 @@ module DLY_SEL_DCODER (
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endmodule
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`endcelldefine
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//
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// DLY_SEL_DECODER black box model
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// Address Decoder
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//
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// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
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//
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`celldefine
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(* blackbox *)
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module DLY_SEL_DECODER (
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input logic DLY_LOAD,
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input logic DLY_ADJ,
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input logic DLY_INCDEC,
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input logic [4:0] DLY_ADDR,
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output reg [2:0] DLY0_CNTRL,
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output reg [2:0] DLY1_CNTRL,
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output reg [2:0] DLY2_CNTRL,
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output reg [2:0] DLY3_CNTRL,
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output reg [2:0] DLY4_CNTRL,
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output reg [2:0] DLY5_CNTRL,
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output reg [2:0] DLY6_CNTRL,
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output reg [2:0] DLY7_CNTRL,
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output reg [2:0] DLY8_CNTRL,
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output reg [2:0] DLY9_CNTRL,
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output reg [2:0] DLY10_CNTRL,
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output reg [2:0] DLY11_CNTRL,
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output reg [2:0] DLY12_CNTRL,
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output reg [2:0] DLY13_CNTRL,
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output reg [2:0] DLY14_CNTRL,
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output reg [2:0] DLY15_CNTRL,
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output reg [2:0] DLY16_CNTRL,
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output reg [2:0] DLY17_CNTRL,
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output reg [2:0] DLY18_CNTRL,
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output reg [2:0] DLY19_CNTRL
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);
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endmodule
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`endcelldefine
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//
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// DLY_VALUE_MUX black box model
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// Multiplexer
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//

‎sim_models/tb/DLY_SEL_DECODER_tb.v‎

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@@ -1,5 +1,5 @@
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module DLY_SEL_DCODER_tb;
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module DLY_SEL_DECODER_tb;
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// Parameters
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@@ -31,7 +31,7 @@ module DLY_SEL_DCODER_tb;
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integer error=0;
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DLY_SEL_DCODER DLY_SEL_DCODER_inst (
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DLY_SEL_DECODER DLY_SEL_DECODER_inst (
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.DLY_LOAD(DLY_LOAD),
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.DLY_ADJ(DLY_ADJ),
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.DLY_INCDEC(DLY_INCDEC),

‎sim_models/verilog/DLY_SEL_DECODER.v‎

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`timescale 1ps/1ps
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`celldefine
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//
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// DLY_SEL_DECODER simulation model
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// Address Decoder
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//
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// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved.
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//
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module DLY_SEL_DECODER (
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input DLY_LOAD, // Delay load input
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input DLY_ADJ, // Delay adjust input
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input DLY_INCDEC, // Delay increment / decrement input
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input [4:0] DLY_ADDR, // Input Address
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output reg [2:0] DLY0_CNTRL, // Output Bus
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output reg [2:0] DLY1_CNTRL, // Output Bus
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output reg [2:0] DLY2_CNTRL, // Output Bus
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output reg [2:0] DLY3_CNTRL, // Output Bus
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output reg [2:0] DLY4_CNTRL, // Output Bus
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output reg [2:0] DLY5_CNTRL, // Output Bus
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output reg [2:0] DLY6_CNTRL, // Output Bus
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output reg [2:0] DLY7_CNTRL, // Output Bus
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output reg [2:0] DLY8_CNTRL, // Output Bus
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output reg [2:0] DLY9_CNTRL, // Output Bus
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output reg [2:0] DLY10_CNTRL, // Output Bus
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output reg [2:0] DLY11_CNTRL, // Output Bus
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output reg [2:0] DLY12_CNTRL, // Output Bus
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output reg [2:0] DLY13_CNTRL, // Output Bus
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output reg [2:0] DLY14_CNTRL, // Output Bus
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output reg [2:0] DLY15_CNTRL, // Output Bus
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output reg [2:0] DLY16_CNTRL, // Output Bus
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output reg [2:0] DLY17_CNTRL, // Output Bus
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output reg [2:0] DLY18_CNTRL, // Output Bus
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output reg [2:0] DLY19_CNTRL // Output Bus
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);
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always @(*)
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begin
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DLY0_CNTRL = 3'b000;
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DLY1_CNTRL = 3'b000;
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DLY2_CNTRL = 3'b000;
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DLY3_CNTRL = 3'b000;
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DLY4_CNTRL = 3'b000;
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DLY5_CNTRL = 3'b000;
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DLY6_CNTRL = 3'b000;
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DLY7_CNTRL = 3'b000;
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DLY8_CNTRL = 3'b000;
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DLY9_CNTRL = 3'b000;
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DLY10_CNTRL = 3'b000;
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DLY11_CNTRL = 3'b000;
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DLY12_CNTRL = 3'b000;
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DLY13_CNTRL = 3'b000;
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DLY14_CNTRL = 3'b000;
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DLY15_CNTRL = 3'b000;
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DLY16_CNTRL = 3'b000;
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DLY17_CNTRL = 3'b000;
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DLY18_CNTRL = 3'b000;
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DLY19_CNTRL = 3'b000;
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case(DLY_ADDR)
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5'd0: DLY0_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd1: DLY1_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd2: DLY2_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd3: DLY3_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd4: DLY4_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd5: DLY5_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd6: DLY6_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd7: DLY7_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd8: DLY8_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd9: DLY9_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd10: DLY10_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd11: DLY11_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd12: DLY12_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd13: DLY13_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd14: DLY14_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd15: DLY15_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd16: DLY16_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd17: DLY17_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd18: DLY18_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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5'd19: DLY19_CNTRL = {DLY_LOAD, DLY_ADJ, DLY_INCDEC};
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endcase
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end
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endmodule
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`endcelldefine

‎tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v‎

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@@ -1,5 +1,5 @@
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module DLY_SEL_DCODER_tb;
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module DLY_SEL_DECODER_tb;
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// Parameters
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@@ -31,7 +31,7 @@ module DLY_SEL_DCODER_tb;
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integer error=0;
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34-
DLY_SEL_DCODER DLY_SEL_DCODER_inst (
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DLY_SEL_DECODER DLY_SEL_DECODER_inst (
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.DLY_LOAD(DLY_LOAD),
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.DLY_ADJ(DLY_ADJ),
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.DLY_INCDEC(DLY_INCDEC),

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