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lines changedSubmodule FPGA_PRIMITIVES_MODELS updated 11 files
- blackbox_models/cell_sim_blackbox.v-36
- sim_models/primitives_mapping/FIFO/fifo18kx2_to_rs_tdp_36k_mapping.v+2-2
- sim_models/primitives_mapping/FIFO/fifo36k_to_rs_tdp_36k_mapping.v+1-1
- sim_models/tb/MIPI_TX_tb.v+1-1
- sim_models/tb/SOC_FPGA_INTF_IRQ_tb.v+51
- sim_models/tb/SOC_FPGA_INTF_JTAG_tb.v+71
- sim_models/verilog/DLY_SEL_DCODER.v-89
- specs_internal/DLY_SEL_DECODER.yaml+144
- specs_internal/DLY_VALUE_MUX.yaml+118
- specs_internal/MIPI_RX.yaml+128
- specs_internal/MIPI_TX.yaml+134
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