@@ -5829,6 +5829,44 @@ static void show_sig(const RTLIL::SigSpec &sig)
58295829 run (" write_verilog -org-name -noattr -noexpr -nohex after_rewire_obuft.v" );
58305830 }
58315831 }
5832+
5833+ // Force 'keep' attribute on original IO BUF cells instantiated at RTL.
5834+ // (ex: EDA-3307 where one I_BUF is removed by optimizer because input is not used)
5835+ //
5836+ void set_iobuf_keep_attribute ()
5837+ {
5838+ for (auto & modules : _design->selected_modules ()) {
5839+
5840+ for (auto & cell : modules->selected_cells ()) {
5841+
5842+ if (cell->type == RTLIL::escape_id (" I_BUF" )) {
5843+ cell->set_bool_attribute (ID::keep);
5844+ continue ;
5845+ }
5846+ if (cell->type == RTLIL::escape_id (" I_BUF_DS" )) {
5847+ cell->set_bool_attribute (ID::keep);
5848+ continue ;
5849+ }
5850+ if (cell->type == RTLIL::escape_id (" O_BUF" )) {
5851+ cell->set_bool_attribute (ID::keep);
5852+ continue ;
5853+ }
5854+ if (cell->type == RTLIL::escape_id (" O_BUF_DS" )) {
5855+ cell->set_bool_attribute (ID::keep);
5856+ continue ;
5857+ }
5858+ if (cell->type == RTLIL::escape_id (" O_BUFT" )) {
5859+ cell->set_bool_attribute (ID::keep);
5860+ continue ;
5861+ }
5862+ if (cell->type == RTLIL::escape_id (" O_BUFT_DS" )) {
5863+ cell->set_bool_attribute (ID::keep);
5864+ continue ;
5865+ }
5866+ }
5867+ }
5868+ }
5869+
58325870 // Map the $TBUF cells into OBUFT equivalent.
58335871 //
58345872 void map_obuft (RTLIL::Module* top_module)
@@ -8491,6 +8529,10 @@ void collect_clocks (RTLIL::Module* module,
84918529 remove_print_cell ();
84928530 illegal_clk_connection ();
84938531
8532+ // set keep attribute on original IO buf cells
8533+ //
8534+ set_iobuf_keep_attribute ();
8535+
84948536 transform (nobram /* bmuxmap */ ); // no "$bmux" mapping in bram state
84958537
84968538#if 1
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