Merge pull request #412 from BessonThierry/main

Fix EDA-3248

Author: alaindargelas

src/synth_rapidsilicon.cc

@@ -464,7 +464,9 @@ struct SynthRapidSiliconPass : public ScriptPass {
 
     // Special cells
     //
-    dict<std::string, pair<int, int>> pp_memories;
+    dict<std::string, pair<int, int>> pp_memories; // pair is width and depth
+    dict<std::string, string> pp_memories_prop;    // property like "dissolved", "rom"
+
 
     // Alias between same signals (for I_BUF/CLK_BUF)
     //
@@ -4208,10 +4210,15 @@ static void show_sig(const RTLIL::SigSpec &sig)
              }
 
              json_file << "     {\n";
-             std::string name = it->first;
+             std::string name = (it->first).substr(1);
              pair<int, int> wd = it->second;
 
-             json_file << "        \"name\" : \"" << name.substr(1) << "\",\n";
+             json_file << "        \"name\" : \"" << name << "\",\n";
+
+             if (pp_memories_prop.count(name)) {
+               json_file << "        \"type\" : \"" << pp_memories_prop[name] << "\",\n";
+             }
+
              json_file << "        \"width\" : \"" << wd.first << "\",\n";
              json_file << "        \"depth\" : \"" << wd.second << "\"\n";
              json_file << "     }";
@@ -4938,6 +4945,25 @@ static void show_sig(const RTLIL::SigSpec &sig)
         }
     }
 
+    // Scratchpad mechanism is used to extract data posted by the call to 
+    // "memory_map". Data give extra memory info like "dissolved", "rom". 
+    //
+    void memoryMapAnalysis() 
+    {
+        dict<std::string, pair<int, int>>::iterator it;
+
+        for (it = pp_memories.begin(); it != pp_memories.end(); ++it) {
+
+             std::string mem_name = it->first;
+             string type = _design->scratchpad_get_string(mem_name);
+
+             if (type.size()) {
+               log("Memory %s type : %s\n", mem_name.c_str(), type.c_str());
+               pp_memories_prop[mem_name.substr(1)] = type;
+             }
+        }
+    }
+
     bool illegal_port_connection(std::set<Cell*>* set_cells){
         bool generic_cell = false;
         bool i_buf = false;
@@ -8099,6 +8125,7 @@ void collect_clocks (RTLIL::Module* module,
 
            if (cell->type.in(ID(I_BUF_DS), ID(O_BUF_DS), ID(O_BUFT_DS), ID(O_SERDES), 
                              ID(I_SERDES), ID(BOOT_CLOCK), ID(O_DELAY), ID(I_DELAY), 
+                             ID(O_SERDES_CLK), ID(PLL),
                              ID(O_BUF), ID(O_BUFT), ID(O_DDR))) {
 
 #if 0
@@ -8837,6 +8864,10 @@ void collect_clocks (RTLIL::Module* module,
 
         run("memory_map");
 
+        // To attach exra info for the netlist info json file
+        //
+        memoryMapAnalysis();
+
         postProcessBrams();
 
         if (check_label("map_gates")) {