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awaisabbas006awaisabbas006
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added comments for DSP inference
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3 files changed

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‎src/rs-dsp-macc.cc‎

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Original file line numberDiff line numberDiff line change
@@ -2,6 +2,29 @@
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* Copyright (C) 2022 RapidSilicon
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*
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*/
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// Awais Abbas
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// The multiplier's output is added to the accumulator's output, and the result from the adder is fed back into the accumulator.
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// this kind of cell structure will be infered as MULTACC
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//
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//
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// _______ ____________
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// | | | |
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// ACC[19:0] `--->| | | | _________
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// | Mult |--------> | | | |___
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// In_B[17:0] ---->| | | |------->|D Q| |---------> output
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// |_______| | | | | |
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// | Add/Neg | | ACC | |
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// | | | | |
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// | | clk-->| | |
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// ACC[63:0] ---->| | |_________| |
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// | | | |
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// | |____________| |
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// | |
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// | |
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// | |
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// |________________________________________|
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include "kernel/modtools.h"

‎src/rs-dsp-multadd.cc‎

Lines changed: 34 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,40 @@
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// Copyright (C) 2022 RapidSilicon
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//
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// Awais Abbas
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// If the multiplier's input is multiplied by a coefficient/constant, and another input is left-shifted, their results are added together,
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// will infer a MULTADD operation for RS_DSP.
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// _______ ____________
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// | | | |
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// Coefficint[19:0] ---->| | | |
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// | Mult |-------------> | |
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// In_B[17:0] ---->| | | |
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// |_______| | |
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// _______ | Adder |-------> output
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// | | | |
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// In_A[19:0] ---->| | | |
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// | Shift |-------------> | |
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// acc_fir[5:0] ---->| Left | | |
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// |_______| |____________|
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//
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// If the accumulator's output is multiplied by the multiplier's second input, and another input is left-shifted, their results are added together,
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// with the adder's output serving as the input to the accumulator, this structure will be infered a MULTADD operation for RS_DSP.
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//
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// ________________________________________________________________
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// | |
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// | _______ ____________ |
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// | | | | | |
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// ACC[19:0] `--->| | | | _________ |
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// | Mult |-------------> | | | |___|-----------------------------> output
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// In_B[17:0] ---->| | | |------->|D Q|
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// |_______| | | | |
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// _______ | Adder | | ACC |
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// | | | | | |
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// In_A[19:0] ---->| | | | clk-->| |
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// | Shift |-------------> | | |_________|
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// acc_fir[5:0] ---->| Left | | |
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// |_______| |____________|
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#include "kernel/yosys.h"
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#include "kernel/modtools.h"
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#include "kernel/ffinit.h"
@@ -74,37 +108,6 @@ struct RsDspMultAddWorker
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continue;
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}
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}
77-
// If the following structure is found in the rtlil model than we can infr a MULTADD for RS-DSP
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// _______ ____________
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// | | | |
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// Coefficint[19:0] ---->| | | |
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// | Mult |-------------> | |
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// In_B[19:0] ---->| | | |
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// |_______| | |
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// _______ | Adder |-------> output
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// | | | |
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// In_A[19:0] ---->| | | |
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// | Shift |-------------> | |
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// acc_fir[5:0] ---->| Left | | |
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// |_______| |____________|
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//
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//
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//
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// ________________________________________________________________
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// | |
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// | _______ ____________ |
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// | | | | | |
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// ACC[19:0] `--->| | | | _________ |
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// | Mult |-------------> | | | |___|-----------------------------> output
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// In_B[19:0] ---->| | | |------->|D Q|
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// |_______| | | | |
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// _______ | Adder | | ACC |
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// | | | | | |
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// In_A[19:0] ---->| | | | clk-->| |
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// | Shift |-------------> | | |_________|
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// acc_fir[5:0] ---->| Left | | |
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// |_______| |____________|
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for (auto &add_cell : add_cells_) {
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add_shl = false;
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add_mul = false;

‎src/synth_rapidsilicon.cc‎

Lines changed: 32 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8782,26 +8782,48 @@ void collect_clocks (RTLIL::Module* module,
87828782
case Technologies::GENESIS_3: {
87838783
#ifdef DEV_BUILD
87848784
run("stat");
8785-
#endif
8785+
#endif
8786+
// rs-dsp-multadd pass will infer multiplier as
8787+
// 1. dsp_t1_20X1864_cfg_ports
8788+
// 2. dsp_t1_10X9X32_cfg_params
8789+
// All the parameters and Ports are configured to support multiply-add (MULTADD) functionality.
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87868791
if (new_dsp19x2) // RUN based on DSP19x2 mapping
87878792
run("rs-dsp-multadd -genesis3 -new_dsp19x2 -max_dsp " + std::to_string(max_dsp));
87888793
else
87898794
run("rs-dsp-multadd -genesis3 -max_dsp " + std::to_string(max_dsp));
87908795

87918796
DSP_COUNTER = DSP_COUNTER + Count_ADD;
87928797
run("wreduce t:$mul");
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8799+
// rs-dsp-multacc pass will infer multiplier as
8800+
// 1. dsp_t1_20X18X64_cfg_ports
8801+
// 2. dsp_t1_10X9X32_cfg_params
8802+
// All the parameters and Ports are configured to support multiply-accumulate (MULTACC) functionality.
8803+
87938804
if (!new_dsp19x2)
87948805
run("rs_dsp_macc" + use_dsp_cfg_params + genesis3 + " -max_dsp " + std::to_string(max_dsp));
87958806
else // RUN based on DSP19x2 mapping
87968807
run("rs_dsp_macc" + use_dsp_cfg_params + genesis3 + " -new_dsp19x2" + " -max_dsp " + std::to_string(max_dsp));
87978808

87988809
check_dsp_device_limit();
87998810

8800-
// Check if mult output is connected with Registers output
8811+
// Check if the multiplier output is connected to a register input before decomposing large multipliers.
8812+
// This function configures the parameters DSP_CLK, DSP_RESET_POL, REGOUT,
8813+
// and DSP_RESET if the corresponding multiplier output Y is connected to a register input.
8814+
// This information is later used during register packing stage of DSP inference.
8815+
88018816
if (tech == Technologies::GENESIS_3)
88028817
check_mult_regout();
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8819+
// Process the large multiplier and decompose it into smaller multipliers optimized for RapidSilicon DSP.
8820+
// The smaller multipliers are then mapped to the following cells.
8821+
// \$__RS_MUL20X18
8822+
// \$__RS_MUL10X9
8823+
88038824
processDsp(cec);
88048825

8826+
// map the processed \$__RS_MUL20X18 and \$__RS_MUL10X9 into dsp_t1_dsp_t1_20X18X64_cfg_ports and dsp_t1_10X9X32_cfg_params.
88058827
if (use_dsp_cfg_params.empty())
88068828
run("techmap -map " + dspMapFile + " -D USE_DSP_CFG_PARAMS=0");
88078829
else
@@ -8827,12 +8849,18 @@ void collect_clocks (RTLIL::Module* module,
88278849
}
88288850
sec_check("after_dsp_map4", true, true);
88298851

8852+
// pack the registers connected to the input and output of multipliers into DSP's
88308853
run("rs-pack-dsp-regs -genesis3");
88318854

88328855
// add register at the remaining decomposed small multiplier that are not packed in DSP cells
88338856
if (tech == Technologies::GENESIS_3)
88348857
add_out_reg();
88358858

8859+
// map the processed DSP cells into following cells based on the mode bits
8860+
// RS_DSP_MULT ,RS_DSP_MULT_REGIN, RS_DSP_MULT_REGOUT, RS_DSP_MULT_REGIN_REGOUT
8861+
// RS_DSP_MULTADD ,RS_DSP_MULTADD_REGIN, RS_DSP_MULTADD_REGOUT, RS_DSP_MULTADD_REGIN_REGOUT
8862+
// RS_DSP_MULTACC ,RS_DSP_MULTACC_REGIN, RS_DSP_MULTACC_REGOUT, RS_DSP_MULTACC_REGIN_REGOUT
8863+
88368864
run("rs_dsp_io_regs -tech genesis3");
88378865

88388866
if (cec) {
@@ -8842,7 +8870,8 @@ void collect_clocks (RTLIL::Module* module,
88428870

88438871

88448872
#if 1
8845-
//run("stat");
8873+
run("stat");
8874+
// finaly mapped above DSP mapped multiplier into DSP38 and DSP19X2
88468875
run("techmap -map " + dsp38MapFile);
88478876
if (new_dsp19x2)
88488877
run("techmap -map " + dsp19x2MapFile);

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