From 9fa2bbc198db045ab03ae4efb8108fd9776c45e5 Mon Sep 17 00:00:00 2001 From: Ayyaz Ahmed Date: Wed, 9 Oct 2024 18:12:40 +0500 Subject: [PATCH 1/2] Release_Sim_1.5.7 --- genesis3/FPGA_PRIMITIVES_MODELS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/genesis3/FPGA_PRIMITIVES_MODELS b/genesis3/FPGA_PRIMITIVES_MODELS index c3b0e742..e6466dbc 160000 --- a/genesis3/FPGA_PRIMITIVES_MODELS +++ b/genesis3/FPGA_PRIMITIVES_MODELS @@ -1 +1 @@ -Subproject commit c3b0e742d194e31bd56d20be4640268b02990197 +Subproject commit e6466dbc19bc2c318a9530e00f3c19e10719b0cc From f7039ec953b1ea19c67ac0305a83f1c99b4928db Mon Sep 17 00:00:00 2001 From: Ayyaz Ahmed Date: Thu, 10 Oct 2024 10:09:00 +0500 Subject: [PATCH 2/2] EDA-3292,corrects illegal O_BUF instantiations --- src/synth_rapidsilicon.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc index 6c0f513a..d5710d1e 100644 --- a/src/synth_rapidsilicon.cc +++ b/src/synth_rapidsilicon.cc @@ -7880,7 +7880,7 @@ void collect_clocks (RTLIL::Module* module, // WARNING; we may need to handle case where 'keep' attribute is on // the I_BUF/O_BUF so that we cannot remove them. // -#if 0 +#if 1 remove_io_buffers(top_module); // Bypass the assigns by replacing LHs by RHS. Assigns will be