Skip to content

Commit 302748e

Browse files
Revert "Disconnecting dangling wires from fabric"
1 parent d63fdf2 commit 302748e

File tree

2 files changed

+7
-5
lines changed

2 files changed

+7
-5
lines changed

CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ set(VERSION_MINOR 0)
1717

1818

1919

20-
set(VERSION_PATCH 383)
20+
set(VERSION_PATCH 382)
2121

2222

2323

design_edit/src/rs_design_edit.cc

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -746,7 +746,6 @@ struct DesignEditRapidSilicon : public ScriptPass {
746746

747747
void handle_dangling_outs(Module *module)
748748
{
749-
std::unordered_set<Wire *> dangling_ins;
750749
for(auto cell : module->cells())
751750
{
752751
for (auto &conn : cell->connections())
@@ -832,9 +831,12 @@ struct DesignEditRapidSilicon : public ScriptPass {
832831
for (SigBit bit : port.second){
833832
if(!used_bits.count(bit) && cell->output(portName)
834833
&& !bit.wire->port_output){
835-
new_ins.erase(bit.wire->name.str());
836-
bit.wire->port_input = false;
837-
dangling_ins.insert(bit.wire);
834+
RTLIL::SigSig new_conn;
835+
RTLIL::Wire *new_wire = module->addWire(NEW_ID, 1);
836+
new_wire->port_output = true;
837+
new_conn.first = new_wire;
838+
new_conn.second = bit;
839+
module->connect(new_conn);
838840
}
839841
}
840842
}

0 commit comments

Comments
 (0)