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Correcting typo
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design_edit/src/rs_design_edit.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -815,7 +815,7 @@ struct DesignEditRapidSilicon : public ScriptPass {
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string module_name = remove_backslashes(cell->type.str());
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if (std::find(primitives.begin(), primitives.end(), module_name) !=
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primitives.end()) {
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//EDA-3010: output primitives cal also have danlging output wire
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//EDA-3010: output primitives can also have danlging output wire
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//bool is_out_prim = (module_name.substr(0, 2) == "O_") ? true : false;
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//if (is_out_prim) continue;
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// Upgrading dangling outs of input primtives to output ports

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