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Handling signals connected to O_FAB and other primitives #825

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Merged
merged 2 commits into from
Dec 5, 2024
Merged

Handling signals connected to O_FAB and other primitives #825

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01aa5da
Handling signals connected to O_FAB and other primitives
behzadmehmood Dec 5, 2024
0bd37c3
Incremented patch version
behzadmehmood Dec 5, 2024
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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ set(VERSION_MINOR 0)



set(VERSION_PATCH 383)
set(VERSION_PATCH 384)



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56 changes: 40 additions & 16 deletions design_edit/src/rs_design_edit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -510,7 +510,8 @@ struct DesignEditRapidSilicon : public ScriptPass {
if (in_bit.wire != nullptr)
{
remove_fab_prims.push_back(cell);
if (fab_ins.count(in_bit) && fab_outs.count(out_bit))
if (new_ins.find(in_bit.wire->name.str()) != new_ins.end() &&
new_outs.find(out_bit.wire->name.str()) != new_outs.end())
{
RTLIL::SigSig new_conn;
new_conn.first = out_bit;
Expand Down Expand Up @@ -541,7 +542,8 @@ struct DesignEditRapidSilicon : public ScriptPass {
if (in_bit.wire != nullptr)
{
remove_fab_prims.push_back(cell);
if (fab_ins.count(in_bit) && fab_outs.count(out_bit))
if (new_ins.find(in_bit.wire->name.str()) != new_ins.end() &&
new_outs.find(out_bit.wire->name.str()) != new_outs.end())
{
RTLIL::SigSig new_conn;
new_conn.first = out_bit;
Expand Down Expand Up @@ -575,6 +577,7 @@ struct DesignEditRapidSilicon : public ScriptPass {
if (cell->type == RTLIL::escape_id("O_FAB") ||
cell->type == RTLIL::escape_id("I_FAB")) continue;

string module_name = remove_backslashes(cell->type.str());
for (auto conn : cell->connections())
{
IdString portName = conn.first;
Expand All @@ -584,22 +587,44 @@ struct DesignEditRapidSilicon : public ScriptPass {
{
if (ofab_sig_map.count(bit))
{
const std::vector<RTLIL::SigBit> outbits = ofab_sig_map[bit];
if(outbits.size() < 1) sigspec.append(bit);
if(outbits.size() == 1)

if ((std::find(primitives.begin(), primitives.end(), module_name) !=
primitives.end()) && cell->input(portName))
{
const std::vector<RTLIL::SigBit> outbits = ofab_sig_map[bit];
RTLIL::SigSig new_conn;
RTLIL::Wire *new_wire = mod->addWire(NEW_ID, 1);
new_outs.erase(bit.wire->name.str());
new_outs.insert(new_wire->name.str());
new_conn.first = new_wire;
new_conn.second = outbits[0];
mod->connect(new_conn);
if (unset_port)
{
cell->unsetPort(portName);
unset_port = false;
}
sigspec.append(outbits[0]);
} else if (outbits.size() > 1)
{
cell->unsetPort(portName);
unset_port = false;
}
sigspec.append(new_wire);
}
else
{
sigspec.append(bit);
if (ofab_conns.find(bit) == ofab_conns.end())
const std::vector<RTLIL::SigBit> outbits = ofab_sig_map[bit];
if(outbits.size() < 1) sigspec.append(bit);
if(outbits.size() == 1)
{
if (unset_port)
{
cell->unsetPort(portName);
unset_port = false;
}
sigspec.append(outbits[0]);
} else if (outbits.size() > 1)
{
ofab_conns.insert({bit, outbits});
sigspec.append(bit);
if (ofab_conns.find(bit) == ofab_conns.end())
{
ofab_conns.insert({bit, outbits});
}
}
}
} else {
Expand Down Expand Up @@ -1683,6 +1708,7 @@ struct DesignEditRapidSilicon : public ScriptPass {
elapsed_time (start, end);
intersection_copy_remove(new_ins, new_outs, interface_wires);
intersect(interface_wires, keep_wires);
remove_io_fab_prim(original_mod);
}

Module *interface_mod = _design->top_module()->clone();
Expand Down Expand Up @@ -1844,8 +1870,6 @@ struct DesignEditRapidSilicon : public ScriptPass {

get_fabric_ios(original_mod);

remove_io_fab_prim(original_mod);

start = high_resolution_clock::now();
log("Deleting non-primitive cells and upgrading wires to ports in interface module\n");
for (auto cell : interface_mod->cells()) {
Expand Down