Merge pull request #8 from os-fpga/virgo_pufs_support

Virgo pufs support

Author: junaidaslam1

boards/rapidsilicon/virgo_proto/virgo_proto.dts

@@ -7,6 +7,7 @@
  /dts-v1/;
 
  #include <rapidsilicon/rapidsi_virgo.dtsi>
+
  /
  {
 	 model = "Rapid Silicon Virgo Proto";
@@ -50,6 +51,14 @@
 	status = "okay";
  };
 
+ &pufs_otp {
+	status = "okay";
+ };
+ 
+ &pufs {
+	status = "okay";
+ };
+ 
  &spi0 {
 	status = "okay";
 	clock-frequency = <26666667>;

boards/rapidsilicon/virgo_proto/virgo_proto_defconfig

@@ -34,4 +34,32 @@ CONFIG_HWINFO_ANDES=n
 # CONFIG_SOC_ANDES_V5_EXECIT=y
 
 # Sys Clock HW Cycles for Virgo Proto used by mtimer
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13333333
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13333333
+
+# Enabling the SPI Peripheral
+CONFIG_SPI=y
+CONFIG_SPI_NOR=y
+
+# Enabling the Crypto Peripheral
+CONFIG_CRYPTO=y
+CONFIG_PUFCC_SECURITY=y
+CONFIG_CRYPTO_PUF_SECURITY=y
+CONFIG_CRYPTO_PUF_SECURITY_OTP=y
+
+# Enabling the DMA Peripheral
+CONFIG_DMA=y
+CONFIG_DMA_ANDES_ATCDMAC100=y
+
+# Enabling the SPI and Flash Peripheral
+CONFIG_FLASH=y
+CONFIG_SPI_NOR_SFDP_DEVICETREE=y
+CONFIG_SPI_ANDES_ATCSPI200=y
+CONFIG_ANDES_SPI_DMA_MODE=n
+
+# Enabling the Counter Peripheral
+CONFIG_COUNTER=y
+CONFIG_COUNTER_ANDES_ATCPIT100=y
+
+# Enabling the Sensor Peripheral
+CONFIG_SENSOR=y
+CONFIG_DTI_PVT=y

drivers/crypto/CMakeLists.txt

@@ -12,4 +12,7 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_NPCX_SHA		crypto_npcx_sha.c)
 zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCHP_XEC_SYMCR	crypto_mchp_xec_symcr.c)
 zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA		crypto_it8xxx2_sha.c)
 zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCUX_DCP		crypto_mcux_dcp.c)
+zephyr_library_sources_ifdef(CONFIG_PUFCC_SECURITY		pufcc.c)
+zephyr_library_sources_ifdef(CONFIG_CRYPTO_PUF_SECURITY crypto_pufs.c)
+zephyr_library_sources_ifdef(CONFIG_CRYPTO_PUF_SECURITY_OTP crypto_pufs_otp.c)
 zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)

drivers/crypto/Kconfig

@@ -77,6 +77,7 @@ source "drivers/crypto/Kconfig.stm32"
 source "drivers/crypto/Kconfig.nrf_ecb"
 source "drivers/crypto/Kconfig.intel"
 source "drivers/crypto/Kconfig.npcx"
+source "drivers/crypto/Kconfig.pufs"
 source "drivers/crypto/Kconfig.xec"
 source "drivers/crypto/Kconfig.it8xxx2"
 source "drivers/crypto/Kconfig.mcux_dcp"

drivers/crypto/Kconfig.pufs

@@ -0,0 +1,34 @@
+# PUF Security Cryptographic Accelerator configuration options
+
+# Copyright (c) 2024 Muhammad Junaid Aslam <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig PUFCC_SECURITY
+	bool "PUF Security Hardware"
+	depends on DT_HAS_PUFSECURITY_PUFCC_ENABLED
+	help
+		Enable PUF Security Hardware.
+
+	if PUFCC_SECURITY
+
+		config RS_RTOS_PORT
+			bool
+
+		config CRYPTO_PUF_SECURITY
+			bool "PUF security Cryptographic Accelerator driver"
+			default n
+			depends on DT_HAS_PUFSECURITY_PUFCC_ENABLED
+			select RS_RTOS_PORT
+			help
+				Enable PUF Security based Cryptographic Accelerator driver.
+
+		config CRYPTO_PUF_SECURITY_OTP
+			bool "PUF security One Time Programmable Memory"
+			default n
+			depends on DT_HAS_PUFSECURITY_OTP_ENABLED
+			select RS_RTOS_PORT
+			help
+				Enable PUF Security based One Time Programmable Memory.
+
+	endif
+