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[feat] add burst support
Signed-off-by: kazutoiris <78157415+kazutoiris@users.noreply.github.com>
1 parent 4957137 commit d965582

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4 files changed

+336
-140
lines changed

4 files changed

+336
-140
lines changed

src/ConstIfc.bsv

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,10 @@ typedef enum {
1010
Precharge,
1111
Init,
1212
Act,
13-
Cmd,
13+
Calc,
14+
StartRead,
15+
WaitRead,
16+
StartWrite,
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Finish,
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Stop
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} StateEnum deriving (Bits, Eq, FShow);
@@ -19,7 +22,7 @@ typedef union tagged {
1922
void Cmd_Nop;
2023
Bit#(9) Cmd_Read;
2124
struct {
22-
Maybe#(Bit#(9)) col;
25+
Bit#(9) col;
2326
Bit#(2) dqm;
2427
Bit#(16) data;
2528
} Cmd_Write;

src/OuterPhy.bsv

Lines changed: 15 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,12 +22,16 @@ interface OuterIfc;
2222
method Bool arValid;
2323
method Bool awValid;
2424
method Bool wValid;
25+
method Bool rRespNotFull;
2526
interface AxiIfc axi;
2627
endinterface
2728

2829
typedef struct {
2930
Bit#(AxiIdWidth) id;
31+
Bit#(1) offset;
32+
Bool replicate;
3033
Bool last;
34+
AXI4_BurstSize burst_size;
3135
} RStatus deriving (Bits, Eq, FShow);
3236

3337
typedef struct {
@@ -51,9 +55,12 @@ instance DefaultValue#(RSplit);
5155
};
5256
endinstance
5357

54-
typedef union tagged {
55-
AXI4_Read_Rq#(AxiAddrWidth, AxiIdWidth, AxiUserWidth) READ_ADDR_REQ;
56-
AXI4_Write_Rq_Addr#(AxiAddrWidth, AxiIdWidth, AxiUserWidth) WRITE_ADDR_REQ;
58+
typedef struct {
59+
Bit#(AxiAddrWidth) addr;
60+
Bit#(AxiIdWidth) id;
61+
AXI4_BurstType burst_type;
62+
AXI4_BurstSize burst_size;
63+
UInt#(8) burst_length;
5764
} AddrReqType deriving (Bits, Eq, FShow);
5865

5966

@@ -69,6 +76,7 @@ module mkOuterPhy(OuterIfc);
6976
FIFOF#(AXI4_Read_Rq#(AxiAddrWidth, AxiIdWidth, AxiUserWidth)) arReqFifo <- mkFIFOF;
7077
FIFOF#(AXI4_Write_Rq_Addr#(AxiAddrWidth, AxiIdWidth, AxiUserWidth)) awReqFifo <- mkFIFOF;
7178
FIFOF#(AXI4_Write_Rq_Data#(AxiDataWidth, AxiUserWidth)) wReqFifo <- mkFIFOF;
79+
FIFOF#(AXI4_Read_Rs#(AxiDataWidth, AxiIdWidth, AxiUserWidth)) rRespFifo <- mkSizedFIFOF(8);
7280

7381
rule arReqFifoEnq;
7482
let d <- s_rd.request.get;
@@ -120,6 +128,10 @@ module mkOuterPhy(OuterIfc);
120128
return wReqFifo.notEmpty;
121129
endmethod
122130

131+
method Bool rRespNotFull;
132+
return rRespFifo.notFull;
133+
endmethod
134+
123135
interface AxiIfc axi;
124136
interface AXI4_Slave_Rd_Fab rd = s_rd.fab;
125137
interface AXI4_Slave_Wr_Fab wr = s_wr.fab;

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