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kazutoiriskazutoiris
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[feat] add fsm
Signed-off-by: kazutoiris <78157415+kazutoiris@users.noreply.github.com>
1 parent fa71972 commit ebaea12

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5 files changed

+245
-69
lines changed

5 files changed

+245
-69
lines changed

‎Makefile‎

Lines changed: 23 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,10 @@ TOP ?= mkSdramController
88
FILE = $(SRC_DIR)/SdramController.bsv
99

1010
TRANSFLAGS = -aggressive-conditions # -lift -split-if
11-
RECOMPILEFLAGS = -u -show-compiles
12-
SCHEDFLAGS = -show-schedule -sched-dot # -show-rule-rel dMemInit_request_put doExecute
11+
RECOMPILE_FLAG = -u -show-compiles
12+
SCHED_FLAG = -show-schedule -sched-dot # -show-rule-rel dMemInit_request_put doExecute
1313
# -show-elab-progress
14-
DEBUGFLAGS = -check-assert \
14+
DEBUG_FLAG = -check-assert \
1515
-continue-after-errors \
1616
-keep-fires \
1717
-keep-inlined-boundaries \
@@ -21,19 +21,21 @@ DEBUGFLAGS = -check-assert \
2121
-show-range-conflict \
2222
-show-stats \
2323
-warn-action-shadowing \
24-
-warn-method-urgency \
25-
-promote-warnings ALL
26-
VERILOGFLAGS = -verilog -remove-dollar -remove-unused-modules # -use-dpi -verilog-filter cmd
27-
BLUESIMFLAGS = -parallel-sim-link 16 # -systemc
28-
OUTDIR = -bdir $(BUILD_DIR) -info-dir $(BUILD_DIR) -simdir $(BUILD_DIR) -vdir $(BUILD_DIR)
29-
WORKDIR = -fdir $(abspath .)
30-
LIBDIR = $(abspath ./lib/BlueAXI/src):$(abspath ./lib/BlueLib/src)
31-
# LIBDIR = %/Libraries/AMBA_TLM3/Axi4:%/Libraries/AMBA_TLM3/TLM3:%/Libraries/AMBA_TLM3/Axi:%/Libraries/Bus
32-
BSVSRC_DIR = -p +:$(abspath $(SRC_DIR)):$(LIBDIR)
33-
DIRFLAGS = $(BSVSRC_DIR) $(OUTDIR) $(WORKDIR)
34-
MISCFLAGS = -show-timestamps -show-version # -steps 1000000000000000 -D macro
35-
RUNTIMEFLAGS = +RTS -K256M -RTS
36-
SIMEXE = $(BUILD_DIR)/out
24+
-warn-method-urgency
25+
VERILOG_FLAG = -verilog -remove-dollar -remove-unused-modules # -use-dpi -verilog-filter cmd
26+
BLUESIM_FLAG = -parallel-sim-link 16 # -systemc
27+
OUT_DIR = -bdir $(BUILD_DIR) -info-dir $(BUILD_DIR) -simdir $(BUILD_DIR) -vdir $(BUILD_DIR)
28+
WORK_DIR = -fdir $(abspath .)
29+
LIB_DIR = $(abspath ./lib/BlueAXI/src):$(abspath ./lib/BlueLib/src)
30+
# LIB_DIR = %/Libraries/AMBA_TLM3/Axi4:%/Libraries/AMBA_TLM3/TLM3:%/Libraries/AMBA_TLM3/Axi:%/Libraries/Bus
31+
BSVSRC_DIR = -p +:$(abspath $(SRC_DIR)):$(LIB_DIR)
32+
DIR_FLAG = $(BSVSRC_DIR) $(OUT_DIR) $(WORK_DIR)
33+
MISCFLAGS = -show-timestamps -show-version \
34+
-promote-warnings ALL \
35+
-suppress-warnings ALL \
36+
# -steps 1000000000000000 -D macro
37+
RUNTIME_FLAG = +RTS -K256M -RTS
38+
SIM_EXE = $(BUILD_DIR)/out
3739

3840
# STA
3941
SDC_FILE ?= $(PWD)/script/top.sdc
@@ -45,17 +47,17 @@ NETLIST_FIXED_V = $(BUILD_DIR)/$(TOP).netlist.fixed.v
4547

4648
build:
4749
@mkdir -p $(BUILD_DIR)
48-
@bsc -elab $(VERILOGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) $(TRANSFLAGS) -g $(TOP) $(FILE)
50+
@bsc -elab $(VERILOG_FLAG) $(DIR_FLAG) $(MISCFLAGS) $(RECOMPILE_FLAG) $(RUNTIME_FLAG) $(TRANSFLAGS) -g $(TOP) $(FILE)
4951
@mkdir -p $(VLOG_DIR)
5052
@bluetcl $(LIST_VLOG) $(BSVSRC_DIR) -bdir $(BUILD_DIR) -vdir $(BUILD_DIR) $(TOP) $(TOP) | grep -i '\.v' | xargs -I {} cp {} $(VLOG_DIR)
5153

5254
test:
5355
@mkdir -p $(BUILD_DIR)
54-
@bsc -elab -sim $(BLUESIMFLAGS) $(DEBUGFLAGS) $(DIRFLAGS) $(MISCFLAGS) $(RECOMPILEFLAGS) $(RUNTIMEFLAGS) -g mkTb $(FILE)
55-
@bsc -sim $(BLUESIMFLAGS) $(DIRFLAGS) $(RECOMPILEFLAGS) -e mkTb -o $(SIMEXE)
56-
$(SIMEXE)
56+
@bsc -elab -sim $(BLUESIM_FLAG) $(DEBUG_FLAG) $(DIR_FLAG) $(MISCFLAGS) $(RECOMPILE_FLAG) $(RUNTIME_FLAG) -g mkTb $(FILE)
57+
@bsc -sim $(BLUESIM_FLAG) $(DIR_FLAG) $(RECOMPILE_FLAG) -e mkTb -o $(SIM_EXE)
58+
$(SIM_EXE)
5759

58-
sta:
60+
sta: build
5961
mkdir -p $(REPORT_DIR)
6062
echo tcl $(SCRIPT_DIR)/yosys.tcl $(TOP) \"$(RTL_FILES)\" $(NETLIST_SYN_V) | yosys -l $(REPORT_DIR)/yosys.log -s -
6163
iEDA -script $(SCRIPT_DIR)/fix-fanout.tcl $(SDC_FILE) $(NETLIST_SYN_V) $(TOP) $(NETLIST_FIXED_V) 2>&1 | tee $(REPORT_DIR)/fix-fanout.log

‎src/ConstIfc.bsv‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ typedef union tagged {
2424
} Cmd_WriteData;
2525
void Cmd_Stop;
2626
Maybe#(Bit#(2)) Cmd_Precharge;
27+
// True for self-refresh, False for auto-refresh
2728
Bool Cmd_Refresh;
2829
void Cmd_RefreshExit;
2930
struct {

‎src/OuterPhy.bsv‎

Lines changed: 52 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ import GetPut::*;
66
typedef 32 AxiAddrWidth;
77
typedef 32 AxiDataWidth;
88
typedef 4 AxiIdWidth;
9-
typedef 4 AxiUserWidth;
9+
typedef 0 AxiUserWidth;
1010

1111
interface AxiIfc;
1212
interface AXI4_Slave_Rd_Fab#(AxiAddrWidth, AxiDataWidth, AxiIdWidth, AxiUserWidth) rd;
@@ -21,9 +21,36 @@ interface OuterIfc;
2121
method Action writeBResp(AXI4_Write_Rs#(AxiIdWidth, AxiUserWidth) resp);
2222
method Bool arValid;
2323
method Bool awValid;
24+
method Bool wValid;
2425
interface AxiIfc axi;
2526
endinterface
2627

28+
typedef struct {
29+
Bit#(AxiIdWidth) id;
30+
Bool last;
31+
} RStatus deriving (Bits, Eq, FShow);
32+
33+
typedef struct {
34+
Bit#(16) data;
35+
RStatus rStatus;
36+
} RSplit deriving (Bits, Eq, FShow);
37+
38+
typedef AXI4_Read_Rs#(AxiDataWidth, AxiIdWidth, AxiUserWidth) RResp;
39+
40+
instance DefaultValue#(RStatus);
41+
defaultValue = RStatus {
42+
id: 0,
43+
last: False
44+
};
45+
endinstance
46+
47+
instance DefaultValue#(RSplit);
48+
defaultValue = RSplit {
49+
data: ?,
50+
rStatus: defaultValue
51+
};
52+
endinstance
53+
2754
typedef union tagged {
2855
AXI4_Read_Rq#(AxiAddrWidth, AxiIdWidth, AxiUserWidth) READ_ADDR_REQ;
2956
AXI4_Write_Rq_Addr#(AxiAddrWidth, AxiIdWidth, AxiUserWidth) WRITE_ADDR_REQ;
@@ -33,17 +60,32 @@ typedef union tagged {
3360

3461
(* synthesize *)
3562
module mkOuterPhy(OuterIfc);
36-
AXI4_Slave_Rd#(AxiAddrWidth, AxiDataWidth, AxiIdWidth, AxiUserWidth) s_rd <- mkAXI4_Slave_Rd_Dummy;
37-
AXI4_Slave_Wr#(AxiAddrWidth, AxiDataWidth, AxiIdWidth, AxiUserWidth) s_wr <- mkAXI4_Slave_Wr_Dummy;
63+
/*
64+
We implemented Pipeline FIFOs in the AR and AW channels ourselves,
65+
so there's no need to buffer the input.
66+
*/
67+
AXI4_Slave_Rd#(AxiAddrWidth, AxiDataWidth, AxiIdWidth, AxiUserWidth) s_rd <- mkAXI4_Slave_Rd(0, 1);
68+
AXI4_Slave_Wr#(AxiAddrWidth, AxiDataWidth, AxiIdWidth, AxiUserWidth) s_wr <- mkAXI4_Slave_Wr(0, 1, 1);
3869

3970
FIFOF#(AXI4_Read_Rq#(AxiAddrWidth, AxiIdWidth, AxiUserWidth)) arReqFifo <- mkFIFOF;
4071
FIFOF#(AXI4_Write_Rq_Addr#(AxiAddrWidth, AxiIdWidth, AxiUserWidth)) awReqFifo <- mkFIFOF;
72+
FIFOF#(AXI4_Write_Rq_Data#(AxiDataWidth, AxiUserWidth)) wReqFifo <- mkFIFOF;
4173

42-
rule arReqFifoRule;
74+
rule arReqFifoEnq;
4375
let d <- s_rd.request.get;
4476
arReqFifo.enq(d);
4577
endrule
4678

79+
rule awReqFifoEnq;
80+
let d <- s_wr.request_addr.get;
81+
awReqFifo.enq(d);
82+
endrule
83+
84+
rule wReqFifoEnq;
85+
let d <- s_wr.request_data.get;
86+
wReqFifo.enq(d);
87+
endrule
88+
4789
method ActionValue#(AXI4_Read_Rq#(AxiAddrWidth, AxiIdWidth, AxiUserWidth)) readArReq;
4890
arReqFifo.deq;
4991
return arReqFifo.first;
@@ -55,8 +97,8 @@ module mkOuterPhy(OuterIfc);
5597
endmethod
5698

5799
method ActionValue#(AXI4_Write_Rq_Data#(AxiAddrWidth, AxiUserWidth)) readWReq;
58-
let d <- s_wr.request_data.get;
59-
return d;
100+
wReqFifo.deq;
101+
return wReqFifo.first;
60102
endmethod
61103

62104
method Action writeRResp(AXI4_Read_Rs#(AxiDataWidth, AxiIdWidth, AxiUserWidth) resp);
@@ -75,6 +117,10 @@ module mkOuterPhy(OuterIfc);
75117
return awReqFifo.notEmpty;
76118
endmethod
77119

120+
method Bool wValid;
121+
return wReqFifo.notEmpty;
122+
endmethod
123+
78124
interface AxiIfc axi;
79125
interface AXI4_Slave_Rd_Fab rd = s_rd.fab;
80126
interface AXI4_Slave_Wr_Fab wr = s_wr.fab;

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