stm32h7-startup: reorder AXI erratum and cache setup

@mkeeter noticed nondeterminism in the delay loop for measurement
handoff, which caused us to realize that it was being performed _before_
the caches were set up ... which means small alignment changes in flash
can have huge impact on the execution time of a tight loop.

While considering fixes, I noticed that the fix for the AXI SRAM read
erratum had gradually drifted below other code. This was safe when I
initially implemented it, because we weren't using AXI SRAM for kernel
stack etc. at the time. We are now!

This commit moves the AXI SRAM erratum fix into pre_init where it runs
before most RAM accesses, and moves cache setup earlier in
system_init_custom to ensure that caches are on for the rest of the
process, including measurement handoff.

Author: cbiffle

drv/stm32h7-startup/src/lib.rs

@@ -52,6 +52,15 @@ unsafe fn system_pre_init() {
 
     // Okay, yay, we can use some RAMs now.
 
+    #[cfg(any(feature = "h743", feature = "h753"))]
+    {
+        // Workaround for erratum 2.2.9 "Reading from AXI SRAM may lead to data
+        // read corruption" - limits AXI SRAM read concurrency.
+        let axi = &*device::AXI::ptr();
+        axi.targ7_fn_mod
+            .modify(|_, w| w.read_iss_override().set_bit());
+    }
+
     // We'll do the rest in system_init.
 }
 
@@ -96,6 +105,11 @@ pub fn system_init_custom(
     // static variables.
     //
     // We are running at 64MHz on the HSI oscillator at voltage scale VOS3.
+    //
+    // Turn on CPU I/D caches to improve performance. This has a significant
+    // impact on the delay loop a few lines below.
+    cp.SCB.enable_icache();
+    cp.SCB.enable_dcache(&mut cp.CPUID);
 
     // Before doing anything else, check for a measurement handoff token
     #[cfg(feature = "measurement-handoff")]
@@ -107,15 +121,6 @@ pub fn system_init_custom(
         });
     }
 
-    #[cfg(any(feature = "h743", feature = "h753"))]
-    {
-        // Workaround for erratum 2.2.9 "Reading from AXI SRAM may lead to data
-        // read corruption" - limits AXI SRAM read concurrency.
-        p.AXI
-            .targ7_fn_mod
-            .modify(|_, w| w.read_iss_override().set_bit());
-    }
-
     // The H7 -- and perhaps the Cortex-M7 -- has the somewhat annoying
     // property that any attempt to use ITM without having TRCENA set in
     // DBGMCU results in the FIFO never being ready (that is, ITM writes
@@ -161,11 +166,6 @@ pub fn system_init_custom(
     // Ethernet is on RMII, not MII.
     p.SYSCFG.pmcr.modify(|_, w| unsafe { w.epis().bits(0b100) });
 
-    // Turn on CPU I/D caches to improve performance at the higher clock speeds
-    // we're about to enable.
-    cp.SCB.enable_icache();
-    cp.SCB.enable_dcache(&mut cp.CPUID);
-
     // The Flash controller comes out of reset configured for 3 wait states.
     // That's approximately correct for 64MHz at VOS3, which is fortunate, since
     // we've been executing instructions out of flash _the whole time._