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Aaron-HartwigAaron-Hartwig
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cosmo-seq: grab latest fpga (#2092)
This will pickup the dimm_regs naming updates to support codegen and remove the extraneous spd_proxy_regs.json file. (oxidecomputer/quartz@62d55cc) Additionally, it adds a post_codes_count register to the eSPI block which will show the number of valid post codes seen. (oxidecomputer/quartz@76b99aa)
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-563
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6 files changed

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‎drv/spartan7-loader/cosmo-seq/README.md‎

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@@ -1,3 +1,3 @@
11
FPGA images and collateral are generated from:
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[this sha](https://github.com/oxidecomputer/quartz/commit/0cf5b6cffba5bbf70db9b50b7301831e7697e8fb)
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[release](https://api.github.com/repos/oxidecomputer/quartz/releases/220433638)
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[this sha](https://github.com/oxidecomputer/quartz/commit/76b99aaf164a4c04d9c88446522b132c0901ff6b)
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[release](https://api.github.com/repos/oxidecomputer/quartz/releases/224921430)

‎drv/spartan7-loader/cosmo-seq/cosmo_seq.bz2‎

-27.7 KB
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‎drv/spartan7-loader/cosmo-seq/cosmo_seq_top.json‎

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@@ -23,7 +23,7 @@
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},
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{
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"type": "addrmap",
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"addr_span_bytes": 36,
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"addr_span_bytes": 40,
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"inst_name": "espi",
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"orig_type_name": "espi_regs",
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"addr_offset": 512,
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{
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"type": "addrmap",
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"addr_span_bytes": 76,
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"inst_name": "spd_proxy",
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"orig_type_name": "spd_proxy_regs",
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"inst_name": "dimms",
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"orig_type_name": "dimm_regs",
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"addr_offset": 1536,
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"children": []
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},

‎drv/spartan7-loader/cosmo-seq/dimm_regs.json‎

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Original file line numberDiff line numberDiff line change
@@ -1,86 +1,13 @@
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{
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"type": "addrmap",
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"addr_span_bytes": 76,
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"inst_name": "spd_proxy_regs",
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"inst_name": "dimm_regs",
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"addr_offset": 0,
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"children": [
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{
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"type": "reg",
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"inst_name": "spd_ctrl",
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"addr_offset": 0,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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"inst_name": "start",
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"lsb": 0,
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"msb": 0,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete."
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "fifo_ctrl",
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"addr_offset": 4,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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"inst_name": "tx_fifo_auto_inc",
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"lsb": 6,
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"msb": 6,
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"reset": 1,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one put TX FIFO in auto increment mode."
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},
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{
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"type": "field",
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"inst_name": "tx_fifo_reset",
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"lsb": 7,
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"msb": 7,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset."
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},
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{
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"type": "field",
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"inst_name": "rx_fifo_auto_inc",
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"lsb": 14,
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"msb": 14,
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"reset": 1,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one put RX FIFO in auto increment mode."
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},
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{
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"type": "field",
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"inst_name": "rx_fifo_reset",
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"lsb": 15,
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"msb": 15,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset."
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "dimm_pcamp",
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"addr_offset": 8,
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"addr_offset": 0,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "spd_present",
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"addr_offset": 12,
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"addr_offset": 4,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "spd_select",
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"addr_offset": 16,
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"addr_offset": 8,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "spd_ctrl",
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"addr_offset": 12,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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"inst_name": "start",
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"lsb": 0,
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"msb": 0,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to initiate a SPD cache read. Cleared by hardware after the read is complete."
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "spd_rd_ptr",
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"addr_offset": 20,
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"addr_offset": 16,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "reg",
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"inst_name": "spd_rdata",
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"addr_offset": 24,
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"addr_offset": 20,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "fifo_ctrl",
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"addr_offset": 24,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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"inst_name": "tx_fifo_auto_inc",
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"lsb": 6,
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"msb": 6,
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"reset": 1,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one put TX FIFO in auto increment mode."
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},
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{
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"type": "field",
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"inst_name": "tx_fifo_reset",
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"lsb": 7,
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"msb": 7,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one to reset TX FIFO. Cleared by hardware after FIFO reset."
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},
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{
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"type": "field",
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"inst_name": "rx_fifo_auto_inc",
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"lsb": 14,
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"msb": 14,
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"reset": 1,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one put RX FIFO in auto increment mode."
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},
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{
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"type": "field",
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"inst_name": "rx_fifo_reset",
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"lsb": 15,
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"msb": 15,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": "Set to one to reset RX FIFO. Cleared by hardware after FIFO reset."
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "bus0_cmd",

‎drv/spartan7-loader/cosmo-seq/espi_regs.json‎

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{
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"type": "addrmap",
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"addr_span_bytes": 36,
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"addr_span_bytes": 40,
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"inst_name": "espi_regs",
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"addr_offset": 0,
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"children": [
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"desc": "MSB is bit 31"
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}
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]
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},
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{
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"type": "reg",
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"inst_name": "post_code_count",
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"addr_offset": 36,
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"regwidth": 32,
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"min_accesswidth": 32,
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"children": [
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{
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"type": "field",
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"inst_name": "count",
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"lsb": 0,
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"msb": 31,
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"reset": 0,
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"sw_access": "rw",
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"se_onread": null,
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"se_onwrite": null,
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"desc": ""
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}
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]
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}
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]
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}

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