Fix Intel CPUID leaf 4 cache topology for SMT

When SMT is enabled, L1/L2 caches should report being shared by 2
logical processors (the SMT siblings). Previously EAX[25:14] was always
being set to 0, indicating no sharing which contradicts the SMT topology
reported in leaf 0xB. As per [1] EAX[25:14] indicates maximum number of
addressable IDs for logical processors sharing this cache.

This mismatch causes linux guest to print "BUG: arch topology borken / the
SMT domain not a subset of the CLS domain" during boot. Linux derives
L2 cache sharing groups from leaf 4 and expects SMT siblings to share
L2 but it was being informed that each vCPU has private L1/L2.

This brings the SMT handling logic in CPUID inline with what being done
for AMD in fix_amd_cache_topo() which sets the sharing count to 2 when
has_smt is true. This fixes #1001.

[1]: Table 1-15. Reference for CPUID Leaf 04H
https://cdrdv2-public.intel.com/775917/intel-64-architecture-processor-topology-enumeration.pdf

Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com>

Author: glitzflitz

lib/propolis/src/cpuid.rs

@@ -337,12 +337,18 @@ impl Specializer {
                         // processor)
                         subleaf.eax |= (num_vproc - 1) << 26;
 
-                        // Present L1 and L2 caches as per-thread, L3 is across
-                        // the whole VM.
+                        // L1/L2 shared by SMT siblings, L3 shared by whole VM.
+                        //
+                        // Per Intel SDM, EAX[25:14] is "Maximum number of
+                        // addressable IDs for logical processors sharing this
+                        // cache". Add one to get the actual count; the nearest
+                        // power of 2 >= that value gives the APIC ID mask width.
                         if level < 3 {
                             subleaf.eax &= !LEAF4_EAX_VCPU_MASK;
-                            // And leave that range 0: this means only one
-                            // vCPU shares the cache.
+                            if self.has_smt {
+                                // 2 logical processors share L1/L2 so (1 + 1) = 2
+                                subleaf.eax |= 1 << 14;
+                            }
                         } else {
                             subleaf.eax &= !LEAF4_EAX_VCPU_MASK;
                             let shifted_vcpu = (num_vcpu - 1) << 14;