Merge pull request #407 from Superhepper/format-zero-missing-tests

Adds tests for vendor specific errors.

Author: wiktor-k

tss-esapi/tests/integration_tests/error_tests/return_code_tests/tpm_tests/mod.rs

@@ -4,5 +4,6 @@
 mod tpm_format_one_argument_number_tests;
 mod tpm_format_one_error_tests;
 mod tpm_format_zero_error_tests;
+mod tpm_format_zero_vendor_specific_tests;
 mod tpm_format_zero_warning_tests;
 mod tpm_response_code_tests;

tss-esapi/tests/integration_tests/error_tests/return_code_tests/tpm_tests/tpm_format_zero_error_tests.rs

@@ -1,5 +1,6 @@
 // Copyright 2022 Contributors to the Parsec project.
 // SPDX-License-Identifier: Apache-2.
+use bitfield::bitfield;
 use std::convert::TryFrom;
 use tss_esapi::{
     constants::{
@@ -145,6 +146,48 @@ fn test_invalid_conversions() {
     );
 }
 
+bitfield! {
+    pub struct ReservedBitHelper(u32);
+    _, set_reserved: 9;
+}
+
+#[test]
+fn test_conversion_of_invalid_value_with_reserved_bits_set() {
+    // Bit 9 In the TPM format zero return code is the reserved bit.
+    // |11|10| 9|   8   | 7| 6| 5| 4| 3| 2| 1| 0|
+    // | W| V| R|TPM 2.0|  |    error number    |
+    let mut helper = ReservedBitHelper(TSS2_TPM_RC_LAYER | TPM2_RC_INITIALIZE);
+    helper.set_reserved(true);
+    let tss_rc_with_reserved_bit_set = helper.0;
+
+    assert_eq!(
+        ReturnCode::try_from(tss_rc_with_reserved_bit_set),
+        Err(Error::WrapperError(WrapperErrorKind::InvalidParam)),
+        "Converting invalid TPM format zero error with reserve bit set did not result in the expected error."
+    );
+}
+
+bitfield! {
+    pub struct Tpm2BitHelper(u32);
+    _, set_tpm_2_0: 8;
+}
+
+#[test]
+fn test_conversion_of_invalid_value_without_tpm2_bit_set() {
+    // Bit 9 In the TPM format zero return code is the reserved bit.
+    // |11|10| 9|   8   | 7| 6| 5| 4| 3| 2| 1| 0|
+    // | W| V| R|TPM 2.0|  |    error number    |
+    let mut helper = Tpm2BitHelper(TSS2_TPM_RC_LAYER | TPM2_RC_INITIALIZE);
+    helper.set_tpm_2_0(false);
+    let tss_rc_with_tpm2_bit_clear = helper.0;
+
+    assert_eq!(
+        ReturnCode::try_from(tss_rc_with_tpm2_bit_clear),
+        Err(Error::WrapperError(WrapperErrorKind::UnsupportedParam)),
+        "Converting invalid TPM format zero error with TPM 2.0 bit clear did not result in the expected error."
+    );
+}
+
 #[test]
 fn test_display_implementation() {
     test_display_trait_impl!(

tss-esapi/tests/integration_tests/error_tests/return_code_tests/tpm_tests/tpm_format_zero_vendor_specific_tests.rs

@@ -0,0 +1,45 @@
+// Copyright 2023 Contributors to the Parsec project.
+// SPDX-License-Identifier: Apache-2.
+use bitfield::bitfield;
+use std::convert::TryFrom;
+use tss_esapi::{
+    constants::tss::{TPM2_RC_INITIALIZE, TSS2_TPM_RC_LAYER},
+    error::{ReturnCode, TpmFormatZeroResponseCode, TpmResponseCode},
+};
+
+bitfield! {
+    pub struct VendorSpecificBitHelper(u32);
+    _, set_is_vendor_specific: 10;
+}
+
+#[test]
+fn test_valid_conversions() {
+    // Bit 10 In the TPM format zero return code is the bit indicating vendor specific.
+    // |11|10| 9|   8   | 7| 6| 5| 4| 3| 2| 1| 0|
+    // | W| V| R|TPM 2.0|  |    error number    |
+    let mut helper = VendorSpecificBitHelper(TSS2_TPM_RC_LAYER | TPM2_RC_INITIALIZE);
+    helper.set_is_vendor_specific(true);
+    let expected_tss_rc = helper.0;
+
+    let actual_rc = ReturnCode::try_from(expected_tss_rc)
+        .expect("Failed to convert TPM zero error return code value with vendor specific bit set into a Result.");
+
+    if let ReturnCode::Tpm(TpmResponseCode::FormatZero(
+        TpmFormatZeroResponseCode::VendorSpecific(actual),
+    )) = actual_rc
+    {
+        assert_eq!(
+            expected_tss_rc,
+            actual.into(),
+            "Converting vendor specific return code did not return the original value."
+        );
+    } else {
+        panic!("TPM TSS2_RC layer did no convert into ReturnCode::Tpm");
+    }
+
+    assert_eq!(
+        expected_tss_rc,
+        actual_rc.into(),
+        "The vendor specific return code did not convert into the expected TSS2_RC in the TPM layer."
+    )
+}