liberty min_pulse_width missing related_pin

jjcherry56 · jjcherry56 · commit 5261a2a91ba5 · 2024-08-09T15:40:21.000-07:00
Signed-off-by: James Cherry &lt;cherry@parallaxsw.com&gt;
diff --git a/liberty/LibertyBuilder.cc b/liberty/LibertyBuilder.cc
@@ -678,6 +678,8 @@ LibertyBuilder::makeMinPulseWidthArcs(LibertyCell *cell,
                                       TimingRole *role,
                                       TimingArcAttrsPtr attrs)
 {
+  if (from_port == nullptr)
+    from_port = to_port;
   TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, related_out,
                                            role, attrs);
   for (auto to_rf : RiseFall::range()) {
diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc
@@ -4119,7 +4119,8 @@ LibertyReader::endTiming(LibertyGroup *group)
     }
     TimingType timing_type = timing_->attrs()->timingType();
     if (timing_->relatedPortNames() == nullptr
-        && !(timing_type == TimingType::min_clock_tree_path
+        && !(timing_type == TimingType::min_pulse_width
+             || timing_type == TimingType::min_clock_tree_path
              || timing_type == TimingType::max_clock_tree_path))
       libWarn(1243, group, "timing group missing related_pin/related_bus_pin.");
   }

Original file line number	Diff line number	Diff line change
`@@ -678,6 +678,8 @@ LibertyBuilder::makeMinPulseWidthArcs(LibertyCell *cell,`
`678`	`678`	`TimingRole *role,`
`679`	`679`	`TimingArcAttrsPtr attrs)`
`680`	`680`	`{`
	`681`	`+ if (from_port == nullptr)`
	`682`	`+ from_port = to_port;`
`681`	`683`	`TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, related_out,`
`682`	`684`	`role, attrs);`
`683`	`685`	`for (auto to_rf : RiseFall::range()) {`
Original file line number	Diff line number	Diff line change
`@@ -4119,7 +4119,8 @@ LibertyReader::endTiming(LibertyGroup *group)`
`4119`	`4119`	`}`
`4120`	`4120`	`TimingType timing_type = timing_->attrs()->timingType();`
`4121`	`4121`	`if (timing_->relatedPortNames() == nullptr`
`4122`		`- && !(timing_type == TimingType::min_clock_tree_path`
	`4122`	`+ && !(timing_type == TimingType::min_pulse_width`
	`4123`	`+ \|\| timing_type == TimingType::min_clock_tree_path`
`4123`	`4124`	`\|\| timing_type == TimingType::max_clock_tree_path))`
`4124`	`4125`	`libWarn(1243, group, "timing group missing related_pin/related_bus_pin.");`
`4125`	`4126`	`}`