How to interpret cell_rise/ cell_fall values of clk input pin in the timing model generated by write_timing_model command

[arunkpv]

Hello!
Asking this query here since I could not find a channel for OpenSTA in open-source-silicon.slack.com

@maliberty , @jjcherry56

I have coded a riscv CPU core in verilog and the top module has only 3 ports: clk: input, reset: input, out[9:0]: output
My objective is to generate a timing lib file for this design at tt corner (library: sky130_fd_sc_hd) using OpenSTA.
So here's what I have done:

1. Generated the post-route netlist using the OpenLane flow
2. Then using this post-route netlist and the same post-CTS SDC file used for the flow,
   perform STA analysis as well as generate the timing lib for the design only for the tt corner.

Accordingly, the following steps were done in OpenSTA:

    define_corners Typical
    read_liberty -corner Typical ~/.volare/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
    
    read_verilog ~/vsd-hdp/OpenLane/designs/riscv_core/runs/run20_wo_latency/results/routing/riscv_core.nl.v
    link_design riscv_core
    
    read_sdc ~/vsd-hdp/OpenLane/designs/riscv_core/src/postcts_wo_latency.sdc
    read_spef ~/vsd-hdp/OpenLane/designs/riscv_core/runs/run20_wo_latency/results/routing/mca/spef/riscv_core.nom.spef
    check_setup -verbose
    
    report_checks -path_delay min_max -fields {nets cap slew input_pins fanout} -digits {5} \
    -corner Typical -group_count 9000000 > a.txt
    
    write_timing_model -corner Typical ./model.lib

• The following is a snapshot of the clock pin details from the lib file.

• My understanding is that the cell_rise(scalar)/ cell_fall(scalar) of the clk pin models the worst clock network delay.

• I grepped for all the clock network delay values in the report_checks output dumped to a.txt [grep "clock network delay " a.txt | sort -nk1 | less]

  • But I was unable to cross-validate the cell_rise/ cell_fall values in the above snapshot with the values in the dump.
  • From the report_checks dump, the clock network delay has a :
    Minimum of: 1.04126ns
    Maximum of: 1.31994ns

Min	Max

So, is my above understanding about the cell_rise/ cell_fall of the clk pin correct ?
If it is correct, how are these values generated by OpenSTA when I do a write_timing_model ?
If not, could you please explain what the cell_rise & cell_fall mean for the clk pin ?

[arunkpv]

Changed the topic title to reflect the basis of the query.

[arunkpv]

As a follow-up to the steps done in the first comment, I tried to manually find the propagation delay from the clk input port to the CLK input pins of all flops in the design.

Since I am only interested in the path delay, I thought I could use the report_dcalc command as follows:

foreach register [all_registers] {
report_dcalc -from [get_full_name [get_ports "clk"]] -to [get_full_name $register]/CLK;
}

• However on executing this command, there is no output shown and no errors as well.
• Is this the proper way to find the delay from the clock input pin to any of the clock sinks ?

[maliberty]

You need to pay attention to

If you are looking for the delay through the cells you would look at the output pins.

[arunkpv]

Hi @maliberty
Thanks for confirming my understanding about the cell_rise/ cell_fall parameter for the clk input pin.

In fact, I did pay attention to the timing_type and it was based on it that I came to a conclusion that cell_rise/cell_fall modelled the clock network latency.

• However, where I got confused was trying to verify whether this understanding was correct or not, by cross-checking against the lowest and highest values of the clock network delay (propagated) reported by report_checks command for all path groups.

• The {min, max}_clock_tree_path values in the lib file were not in agreement with the lowest & highest values of the clock network delay reported by report_checks for all clock sinks. (please see snapshots at the end of the first comment)

  • Is this methodology that I have followed wrong ?

• Also, how do I check the clock path delay, say from the clk input port to some FF CLK pin, manually using OpenSTA commands ?
  Can report_dcalc command be used for this (like I have tried in comment 3) ?

[jjcherry56]

report_dcalc is irrelevant. It reports delay calculation for a single gate.
The command you are looking for is report_clock_latency.
But please do not ask questions about specifics without providing a testcase.
The details always matter and diagrams and english descriptions don't run on my machine.

[maliberty]

I think you are better off opening an issue with an actual test case as this is hard to diagnose from screen shots.

[arunkpv]

Hi @maliberty, @jjcherry56

I refrained from opening a GitHub issue and initiated a discussion thread instead so that I could at least confirm if what I was doing was correct or not before proceeding.

I don't think opening a GitHub issue is required now.
The disagreement in the values in the written lib file and clock network delay from report_checks command output is related the OpenSTA versions being used.

Previously I was using the following OpenSTA builds:

• Standalone: OpenSTA 2.4.0 3e2295adfd (Built from GitHub source circa early November, 2023)
• Included in OpenLane: OpenSTA 2.4.0 0889970d17 (OpenLane version 2719508edbb579ab7317d1e0942b774d8d4aa214, built around Mid-March, 2024)
  • With these versions, the shell reported report_clock_latency as an invalid command, and,
    the cell_rise value for clk pin in the generated lib file mismatches with the lowest and highest values from report_checks dump. (this comparison is the only way I could do any cross-checks in these versions)

I just now built the latest version from GitHub source OpenSTA 2.5.0 a7f34210b4
And with this version:

• The shell recognizes the report_clock_latency command
• Following all three data points are in agreement:
  • rise -> rise clk network latency reported by report_clock_latency command
  • cell_rise values in the generated lib file, and
  • lowest (1.04126) & highest (1.31994) values of clock network delay from the report_checks dump

Thanks very much for helping to take a look into this!
Closing this thread.

---

PS: In case you are interested, the attached opensta_timing_model_issue.zip file contains all the required files to repro.

Attaching the below only for information:
1)

2)

3)

4) report_checks_dump_openlane_opensta_v2.4.0.txt

5) report_checks_dump_opensta_v2.5.0.txt