Liberty issue: `statetable` should support bundles properly

[akashlevy]

Suppose you have a bundle D with members D1 and D2. If you try to use D directly in a Liberty statetable, you get the warning:

statetable input port D not found

This was something I discovered in an MBFF in a commercial library. This should probably be supported properly.

[akashlevy]

Let me know if any more info is needed to triage this. I can't share the original test case for obvious reasons, but I'm happy to construct a small test case if that would be helpful.

[akashlevy]

@jjcherry56 are statetables used for anything besides cell equivalence? If not, can I safely ignore this warning?

[jjcherry56]

LibertyCell::hasSequentials()

The existence but not contents matters in a few places.

[akashlevy]

Got it. I'll leave this issue open though, since it should not produce a warning. But this is low priority

[jjcherry56]

It would help if you can produce a small testcase

[akashlevy]

library (mb_statetable_cell_library) {
	capacitive_load_unit (1.0,fF);
	current_unit : "1mA";
	delay_model : "table_lookup";
	input_threshold_pct_fall : 50.0;
	input_threshold_pct_rise : 50.0;
	leakage_power_unit : "1pW";
	nom_process : 1.0;
	nom_temperature : 0.0;
	nom_voltage : 1.0;
	output_threshold_pct_fall : 50.0;
	output_threshold_pct_rise : 50.0;
	pulling_resistance_unit : "1kohm";
	simulation : 0;
	slew_derate_from_library : 1.0;
	slew_lower_threshold_pct_fall : 30.0;
	slew_lower_threshold_pct_rise : 30.0;
	slew_upper_threshold_pct_fall : 70.0;
	slew_upper_threshold_pct_rise : 70.0;
	time_unit : "1ps";
	voltage_unit : "1v";
	default_input_pin_cap : 1.0;	
	cell (mb_statetable_cell) {
		pin_name_map("CP", \
			"D1", \
			"D2", \
			"SE", \
			"SI", \
			"SO", \
			"Z");
		area : 1;
		statetable ("CP SE SI D","IQ IQN") {
			table : "R L - L : - - : L H,               R H L - : - - : L H,               R L - H : - - : H L,               R H H - : - - : H L,              ~R - - - : - - : N N";
			power_down_function : "!VDD+VSS";
		}
		pg_pin (VDD) {
			voltage_name : "VDD";
			pg_type : "primary_power";
			related_bias_pin : "VPP";
		}
		pg_pin (VSS) {
			voltage_name : "VSS";
			pg_type : "primary_ground";
			related_bias_pin : "VBB";
		}
		pin (CP) {
			capacitance : 1;
			clock : true;
			direction : "input";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
		}
		pin (D1) {
			capacitance : 1;
			direction : "input";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
		}
		pin (D2) {
			capacitance : 1;
			direction : "input";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
		}
		pin (IQ1) {
			direction : "internal";
			input_map : "CP SE SI D1";
			internal_node : "IQ";
			inverted_output : false;
		}
		pin (IQ2) {
			direction : "internal";
			input_map : "CP SE IQ1 D2";
			internal_node : "IQ";
			inverted_output : false;
		}
		pin (SE) {
			capacitance : 1;
			direction : "input";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
		}
		pin (SI) {
			capacitance : 1;
			direction : "input";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
		}
		pin (SO) {
			direction : "output";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
			state_function : "IQ2";
			power_down_function : "!VDD+VSS";
		}
		pin (Z) {
			direction : "output";
			related_ground_pin : "VSS";
			related_power_pin : "VDD";
			state_function : "((!CP IQ1) + (CP IQ2))";
			power_down_function : "!VDD+VSS";
		}
		test_cell () {
			ff_bank (IIQ,IIQN,2) {
				clocked_on : "CP";
				next_state : "D";
			}
			bundle (IQ) {
				members("IQ1", \
					"IQ2");
				direction : "internal";
				function : "IIQ";
			}
			bundle (D) {
				members("D1", \
					"D2");
				direction : "input";
			}
			pin (CP) {
				direction : "input";
			}
			pin (SI) {
				direction : "input";
				signal_type : "test_scan_in";
			}
			pin (SE) {
				direction : "input";
				signal_type : "test_scan_enable";
			}
			pin (SO) {
				direction : "output";
				state_function : "IQ2";
				signal_type : "test_scan_out";
				test_output_only : true;
			}
			pin (Z) {
				direction : "output";
				state_function : "((CP' IQ1) + (CP IQ2))";
			}
		}
	}
}

[akashlevy]

Looking more closely, it seems that the bundle is defined in a test_cell, and the bundle encapsulates two pins that are described outside the test_cell.

[jjcherry56]

Ya, that's weird. Technically the test_cell is "inside" the cell that includes the scan (not the way I would have defined it, but this apparently how liberty works). So the cell needs to inherit the bundle.

[akashlevy]

Yep, some of these commercial libs have weird stuff