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[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM (llvm#121464)
1 parent f024708 commit 1547382

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6 files changed

+2928
-125
lines changed

6 files changed

+2928
-125
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -402,6 +402,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
402402
case ISD::FMAXNUM_IEEE:
403403
case ISD::FMINIMUM:
404404
case ISD::FMAXIMUM:
405+
case ISD::FMINIMUMNUM:
406+
case ISD::FMAXIMUMNUM:
405407
case ISD::FCOPYSIGN:
406408
case ISD::FSQRT:
407409
case ISD::FSIN:
@@ -1081,6 +1083,10 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
10811083
case ISD::FMAXIMUM:
10821084
Results.push_back(TLI.expandFMINIMUM_FMAXIMUM(Node, DAG));
10831085
return;
1086+
case ISD::FMINIMUMNUM:
1087+
case ISD::FMAXIMUMNUM:
1088+
Results.push_back(TLI.expandFMINIMUMNUM_FMAXIMUMNUM(Node, DAG));
1089+
return;
10841090
case ISD::SMIN:
10851091
case ISD::SMAX:
10861092
case ISD::UMIN:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
149149
case ISD::FMAXNUM_IEEE:
150150
case ISD::FMINIMUM:
151151
case ISD::FMAXIMUM:
152+
case ISD::FMINIMUMNUM:
153+
case ISD::FMAXIMUMNUM:
152154
case ISD::FLDEXP:
153155
case ISD::ABDS:
154156
case ISD::ABDU:

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 35 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -632,6 +632,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
632632
setOperationAction(ISD::FMAXNUM, VT, Action);
633633
setOperationAction(ISD::FMINIMUM, VT, Action);
634634
setOperationAction(ISD::FMAXIMUM, VT, Action);
635+
setOperationAction(ISD::FMINIMUMNUM, VT, Action);
636+
setOperationAction(ISD::FMAXIMUMNUM, VT, Action);
635637
setOperationAction(ISD::FSIN, VT, Action);
636638
setOperationAction(ISD::FCOS, VT, Action);
637639
setOperationAction(ISD::FSINCOS, VT, Action);
@@ -1075,6 +1077,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
10751077

10761078
setOperationAction(ISD::FMAXIMUM, MVT::f32, Custom);
10771079
setOperationAction(ISD::FMINIMUM, MVT::f32, Custom);
1080+
setOperationAction(ISD::FMAXIMUMNUM, MVT::f32, Custom);
1081+
setOperationAction(ISD::FMINIMUMNUM, MVT::f32, Custom);
10781082

10791083
setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
10801084
setOperationAction(ISD::FABS, MVT::v4f32, Custom);
@@ -1117,6 +1121,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
11171121
for (auto VT : { MVT::f64, MVT::v4f32, MVT::v2f64 }) {
11181122
setOperationAction(ISD::FMAXIMUM, VT, Custom);
11191123
setOperationAction(ISD::FMINIMUM, VT, Custom);
1124+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
1125+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
11201126
}
11211127

11221128
for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
@@ -1482,6 +1488,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14821488

14831489
setOperationAction(ISD::FMAXIMUM, VT, Custom);
14841490
setOperationAction(ISD::FMINIMUM, VT, Custom);
1491+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
1492+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
14851493
setOperationAction(ISD::FCANONICALIZE, VT, Custom);
14861494
}
14871495

@@ -1827,6 +1835,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
18271835
for (MVT VT : { MVT::v16f32, MVT::v8f64 }) {
18281836
setOperationAction(ISD::FMAXIMUM, VT, Custom);
18291837
setOperationAction(ISD::FMINIMUM, VT, Custom);
1838+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
1839+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
18301840
setOperationAction(ISD::FNEG, VT, Custom);
18311841
setOperationAction(ISD::FABS, VT, Custom);
18321842
setOperationAction(ISD::FMA, VT, Legal);
@@ -2298,6 +2308,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
22982308
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
22992309
setOperationAction(ISD::FMAXIMUM, MVT::f16, Custom);
23002310
setOperationAction(ISD::FMINIMUM, MVT::f16, Custom);
2311+
setOperationAction(ISD::FMAXIMUMNUM, MVT::f16, Custom);
2312+
setOperationAction(ISD::FMINIMUMNUM, MVT::f16, Custom);
23012313
setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
23022314
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
23032315

@@ -2345,6 +2357,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
23452357

23462358
setOperationAction(ISD::FMINIMUM, MVT::v32f16, Custom);
23472359
setOperationAction(ISD::FMAXIMUM, MVT::v32f16, Custom);
2360+
setOperationAction(ISD::FMINIMUMNUM, MVT::v32f16, Custom);
2361+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v32f16, Custom);
23482362
}
23492363

23502364
if (Subtarget.hasVLX()) {
@@ -2392,9 +2406,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
23922406

23932407
setOperationAction(ISD::FMINIMUM, MVT::v8f16, Custom);
23942408
setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Custom);
2409+
setOperationAction(ISD::FMINIMUMNUM, MVT::v8f16, Custom);
2410+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v8f16, Custom);
23952411

23962412
setOperationAction(ISD::FMINIMUM, MVT::v16f16, Custom);
23972413
setOperationAction(ISD::FMAXIMUM, MVT::v16f16, Custom);
2414+
setOperationAction(ISD::FMINIMUMNUM, MVT::v16f16, Custom);
2415+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v16f16, Custom);
23982416
}
23992417
}
24002418

@@ -2453,6 +2471,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
24532471
setOperationAction(ISD::SETCC, VT, Custom);
24542472
setOperationAction(ISD::FMINIMUM, VT, Custom);
24552473
setOperationAction(ISD::FMAXIMUM, VT, Custom);
2474+
setOperationAction(ISD::FMINIMUMNUM, VT, Custom);
2475+
setOperationAction(ISD::FMAXIMUMNUM, VT, Custom);
24562476
}
24572477
if (Subtarget.hasAVX10_2_512()) {
24582478
setOperationAction(ISD::FADD, MVT::v32bf16, Legal);
@@ -2464,6 +2484,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
24642484
setOperationAction(ISD::SETCC, MVT::v32bf16, Custom);
24652485
setOperationAction(ISD::FMINIMUM, MVT::v32bf16, Custom);
24662486
setOperationAction(ISD::FMAXIMUM, MVT::v32bf16, Custom);
2487+
setOperationAction(ISD::FMINIMUMNUM, MVT::v32bf16, Custom);
2488+
setOperationAction(ISD::FMAXIMUMNUM, MVT::v32bf16, Custom);
24672489
}
24682490
for (auto VT : {MVT::f16, MVT::f32, MVT::f64}) {
24692491
setCondCodeAction(ISD::SETOEQ, VT, Custom);
@@ -28850,13 +28872,15 @@ static SDValue LowerMINMAX(SDValue Op, const X86Subtarget &Subtarget,
2885028872

2885128873
static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2885228874
SelectionDAG &DAG) {
28853-
assert((Op.getOpcode() == ISD::FMAXIMUM || Op.getOpcode() == ISD::FMINIMUM) &&
28854-
"Expected FMAXIMUM or FMINIMUM opcode");
2885528875
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2885628876
EVT VT = Op.getValueType();
2885728877
SDValue X = Op.getOperand(0);
2885828878
SDValue Y = Op.getOperand(1);
2885928879
SDLoc DL(Op);
28880+
bool IsMaxOp =
28881+
Op.getOpcode() == ISD::FMAXIMUM || Op.getOpcode() == ISD::FMAXIMUMNUM;
28882+
bool IsNum =
28883+
Op.getOpcode() == ISD::FMINIMUMNUM || Op.getOpcode() == ISD::FMAXIMUMNUM;
2886028884
if (Subtarget.hasAVX10_2() && TLI.isTypeLegal(VT)) {
2886128885
unsigned Opc = 0;
2886228886
if (VT.isVector())
@@ -28866,7 +28890,7 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2886628890

2886728891
if (Opc) {
2886828892
SDValue Imm =
28869-
DAG.getTargetConstant(Op.getOpcode() == ISD::FMAXIMUM, DL, MVT::i32);
28893+
DAG.getTargetConstant(IsMaxOp + (IsNum ? 16 : 0), DL, MVT::i32);
2887028894
return DAG.getNode(Opc, DL, VT, X, Y, Imm, Op->getFlags());
2887128895
}
2887228896
}
@@ -28876,7 +28900,7 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2887628900
APInt OppositeZero = PreferredZero;
2887728901
EVT IVT = VT.changeTypeToInteger();
2887828902
X86ISD::NodeType MinMaxOp;
28879-
if (Op.getOpcode() == ISD::FMAXIMUM) {
28903+
if (IsMaxOp) {
2888028904
MinMaxOp = X86ISD::FMAX;
2888128905
OppositeZero.setSignBit();
2888228906
} else {
@@ -29006,7 +29030,9 @@ static SDValue LowerFMINIMUM_FMAXIMUM(SDValue Op, const X86Subtarget &Subtarget,
2900629030
if (IgnoreNaN || DAG.isKnownNeverNaN(NewX))
2900729031
return MinMax;
2900829032

29009-
SDValue IsNaN = DAG.getSetCC(DL, SetCCType, NewX, NewX, ISD::SETUO);
29033+
SDValue IsNaN =
29034+
DAG.getSetCC(DL, SetCCType, NewX, NewX, IsNum ? ISD::SETO : ISD::SETUO);
29035+
2901029036
return DAG.getSelect(DL, VT, IsNaN, NewX, MinMax);
2901129037
}
2901229038

@@ -33264,6 +33290,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3326433290
case ISD::UMIN: return LowerMINMAX(Op, Subtarget, DAG);
3326533291
case ISD::FMINIMUM:
3326633292
case ISD::FMAXIMUM:
33293+
case ISD::FMINIMUMNUM:
33294+
case ISD::FMAXIMUMNUM:
3326733295
return LowerFMINIMUM_FMAXIMUM(Op, Subtarget, DAG);
3326833296
case ISD::ABS: return LowerABS(Op, Subtarget, DAG);
3326933297
case ISD::ABDS:
@@ -46027,6 +46055,8 @@ static SDValue scalarizeExtEltFP(SDNode *ExtElt, SelectionDAG &DAG,
4602746055
case ISD::FMAXNUM_IEEE:
4602846056
case ISD::FMAXIMUM:
4602946057
case ISD::FMINIMUM:
46058+
case ISD::FMAXIMUMNUM:
46059+
case ISD::FMINIMUMNUM:
4603046060
case X86ISD::FMAX:
4603146061
case X86ISD::FMIN:
4603246062
case ISD::FABS: // Begin 1 operand

‎llvm/test/CodeGen/AMDGPU/maximumnum.ll‎

Lines changed: 60 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1838,11 +1838,11 @@ define <3 x half> @v_maximumnum_v3f16(<3 x half> %x, <3 x half> %y) {
18381838
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
18391839
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
18401840
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1841-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1842-
; GFX8-NEXT: v_max_f16_e32 v2, v3, v3
1841+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
18431842
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
1843+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1844+
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
18441845
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
1845-
; GFX8-NEXT: v_max_f16_e32 v1, v1, v2
18461846
; GFX8-NEXT: s_setpc_b64 s[30:31]
18471847
;
18481848
; GFX9-LABEL: v_maximumnum_v3f16:
@@ -1904,8 +1904,8 @@ define <3 x half> @v_maximumnum_v3f16_nnan(<3 x half> %x, <3 x half> %y) {
19041904
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19051905
; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
19061906
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1907-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
19081907
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
1908+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
19091909
; GFX8-NEXT: s_setpc_b64 s[30:31]
19101910
;
19111911
; GFX9-LABEL: v_maximumnum_v3f16_nnan:
@@ -1947,20 +1947,20 @@ define <4 x half> @v_maximumnum_v4f16(<4 x half> %x, <4 x half> %y) {
19471947
; GFX8-LABEL: v_maximumnum_v4f16:
19481948
; GFX8: ; %bb.0:
19491949
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1950-
; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1951-
; GFX8-NEXT: v_max_f16_sdwa v5, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1952-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
1953-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
1950+
; GFX8-NEXT: v_max_f16_sdwa v4, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1951+
; GFX8-NEXT: v_max_f16_sdwa v5, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
19541952
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1955-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1956-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
1957-
; GFX8-NEXT: v_max_f16_sdwa v2, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1958-
; GFX8-NEXT: v_max_f16_sdwa v4, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1953+
; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
1954+
; GFX8-NEXT: v_max_f16_sdwa v6, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
19591955
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
19601956
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
1961-
; GFX8-NEXT: v_max_f16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1957+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
1958+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
1959+
; GFX8-NEXT: v_max_f16_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
19621960
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
1963-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
1961+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
1962+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
1963+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
19641964
; GFX8-NEXT: s_setpc_b64 s[30:31]
19651965
;
19661966
; GFX9-LABEL: v_maximumnum_v4f16:
@@ -2020,12 +2020,12 @@ define <4 x half> @v_maximumnum_v4f16_nnan(<4 x half> %x, <4 x half> %y) {
20202020
; GFX8-LABEL: v_maximumnum_v4f16_nnan:
20212021
; GFX8: ; %bb.0:
20222022
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2023-
; GFX8-NEXT: v_max_f16_sdwa v4, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2024-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
2025-
; GFX8-NEXT: v_max_f16_sdwa v2, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2023+
; GFX8-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2024+
; GFX8-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
20262025
; GFX8-NEXT: v_max_f16_e32 v1, v1, v3
2027-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
2028-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
2026+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
2027+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v5
2028+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
20292029
; GFX8-NEXT: s_setpc_b64 s[30:31]
20302030
;
20312031
; GFX9-LABEL: v_maximumnum_v4f16_nnan:
@@ -2067,27 +2067,27 @@ define <6 x half> @v_maximumnum_v6f16(<6 x half> %x, <6 x half> %y) {
20672067
; GFX8-LABEL: v_maximumnum_v6f16:
20682068
; GFX8: ; %bb.0:
20692069
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2070-
; GFX8-NEXT: v_max_f16_sdwa v6, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2071-
; GFX8-NEXT: v_max_f16_sdwa v7, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2072-
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2073-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2070+
; GFX8-NEXT: v_max_f16_sdwa v6, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2071+
; GFX8-NEXT: v_max_f16_sdwa v7, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
20742072
; GFX8-NEXT: v_max_f16_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2075-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
2076-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
2077-
; GFX8-NEXT: v_max_f16_sdwa v3, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2078-
; GFX8-NEXT: v_max_f16_sdwa v6, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2073+
; GFX8-NEXT: v_max_f16_sdwa v7, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2074+
; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2075+
; GFX8-NEXT: v_max_f16_sdwa v7, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2076+
; GFX8-NEXT: v_max_f16_sdwa v8, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2077+
; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2078+
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
2079+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
20792080
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
20802081
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
2081-
; GFX8-NEXT: v_max_f16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2082+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2083+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2084+
; GFX8-NEXT: v_max_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2085+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v5
20822086
; GFX8-NEXT: v_max_f16_e32 v1, v1, v4
2083-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
2084-
; GFX8-NEXT: v_max_f16_sdwa v3, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2085-
; GFX8-NEXT: v_max_f16_sdwa v4, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2086-
; GFX8-NEXT: v_max_f16_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2087-
; GFX8-NEXT: v_max_f16_e32 v4, v5, v5
2088-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
2089-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v4
2090-
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
2087+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
2088+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
2089+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v7
2090+
; GFX8-NEXT: v_or_b32_e32 v2, v2, v6
20912091
; GFX8-NEXT: s_setpc_b64 s[30:31]
20922092
;
20932093
; GFX9-LABEL: v_maximumnum_v6f16:
@@ -2159,34 +2159,34 @@ define <8 x half> @v_maximumnum_v8f16(<8 x half> %x, <8 x half> %y) {
21592159
; GFX8-LABEL: v_maximumnum_v8f16:
21602160
; GFX8: ; %bb.0:
21612161
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2162-
; GFX8-NEXT: v_max_f16_sdwa v8, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2163-
; GFX8-NEXT: v_max_f16_sdwa v9, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2164-
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
2165-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2162+
; GFX8-NEXT: v_max_f16_sdwa v8, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2163+
; GFX8-NEXT: v_max_f16_sdwa v9, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
21662164
; GFX8-NEXT: v_max_f16_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2167-
; GFX8-NEXT: v_max_f16_e32 v0, v0, v4
2168-
; GFX8-NEXT: v_or_b32_e32 v0, v0, v8
2169-
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2170-
; GFX8-NEXT: v_max_f16_sdwa v8, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2165+
; GFX8-NEXT: v_max_f16_sdwa v9, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2166+
; GFX8-NEXT: v_max_f16_sdwa v10, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2167+
; GFX8-NEXT: v_max_f16_sdwa v9, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2168+
; GFX8-NEXT: v_max_f16_sdwa v10, v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2169+
; GFX8-NEXT: v_max_f16_sdwa v11, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2170+
; GFX8-NEXT: v_max_f16_sdwa v10, v11, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2171+
; GFX8-NEXT: v_max_f16_sdwa v11, v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2172+
; GFX8-NEXT: v_max_f16_sdwa v12, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2173+
; GFX8-NEXT: v_max_f16_e32 v7, v7, v7
2174+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2175+
; GFX8-NEXT: v_max_f16_e32 v6, v6, v6
2176+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
21712177
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
21722178
; GFX8-NEXT: v_max_f16_e32 v1, v1, v1
2173-
; GFX8-NEXT: v_max_f16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2179+
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
2180+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
2181+
; GFX8-NEXT: v_max_f16_sdwa v11, v12, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2182+
; GFX8-NEXT: v_max_f16_e32 v3, v3, v7
2183+
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
21742184
; GFX8-NEXT: v_max_f16_e32 v1, v1, v5
2175-
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
2176-
; GFX8-NEXT: v_max_f16_sdwa v4, v6, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2177-
; GFX8-NEXT: v_max_f16_sdwa v5, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2178-
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2179-
; GFX8-NEXT: v_max_f16_e32 v5, v6, v6
2180-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
2181-
; GFX8-NEXT: v_max_f16_e32 v2, v2, v5
2182-
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
2183-
; GFX8-NEXT: v_max_f16_sdwa v4, v7, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2184-
; GFX8-NEXT: v_max_f16_sdwa v5, v3, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
2185-
; GFX8-NEXT: v_max_f16_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
2186-
; GFX8-NEXT: v_max_f16_e32 v5, v7, v7
2187-
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
2188-
; GFX8-NEXT: v_max_f16_e32 v3, v3, v5
2189-
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
2185+
; GFX8-NEXT: v_max_f16_e32 v0, v0, v4
2186+
; GFX8-NEXT: v_or_b32_e32 v0, v0, v11
2187+
; GFX8-NEXT: v_or_b32_e32 v1, v1, v10
2188+
; GFX8-NEXT: v_or_b32_e32 v2, v2, v9
2189+
; GFX8-NEXT: v_or_b32_e32 v3, v3, v8
21902190
; GFX8-NEXT: s_setpc_b64 s[30:31]
21912191
;
21922192
; GFX9-LABEL: v_maximumnum_v8f16:

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