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AMDGPU: Mark workitem ID intrinsics with range attribute (llvm#136196)
This avoids the need to have special handling at every use site. Unfortunately this means we unnecessarily emit AssertZext in the DAG (where we already directly understand the range of the intrinsic), andt we regress in undefined cases as we don't fold out asserts on undef.
1 parent 31ddaef commit 9bdd9dc

19 files changed

+218
-202
lines changed

‎clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp‎

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -171,16 +171,6 @@ static Value *emitFPIntBuiltin(CodeGenFunction &CGF,
171171
return CGF.Builder.CreateCall(F, {Src0, Src1});
172172
}
173173

174-
static Value *emitRangedBuiltin(CodeGenFunction &CGF, unsigned IntrinsicID,
175-
int low, int high) {
176-
Function *F = CGF.CGM.getIntrinsic(IntrinsicID, {});
177-
llvm::CallInst *Call = CGF.Builder.CreateCall(F);
178-
llvm::ConstantRange CR(APInt(32, low), APInt(32, high));
179-
Call->addRangeRetAttr(CR);
180-
Call->addRetAttr(llvm::Attribute::AttrKind::NoUndef);
181-
return Call;
182-
}
183-
184174
// For processing memory ordering and memory scope arguments of various
185175
// amdgcn builtins.
186176
// \p Order takes a C++11 comptabile memory-ordering specifier and converts
@@ -934,15 +924,6 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
934924
Function *F = CGM.getIntrinsic(BuiltinWMMAOp, ArgTypes);
935925
return Builder.CreateCall(F, Args);
936926
}
937-
938-
// amdgcn workitem
939-
case AMDGPU::BI__builtin_amdgcn_workitem_id_x:
940-
return emitRangedBuiltin(*this, Intrinsic::amdgcn_workitem_id_x, 0, 1024);
941-
case AMDGPU::BI__builtin_amdgcn_workitem_id_y:
942-
return emitRangedBuiltin(*this, Intrinsic::amdgcn_workitem_id_y, 0, 1024);
943-
case AMDGPU::BI__builtin_amdgcn_workitem_id_z:
944-
return emitRangedBuiltin(*this, Intrinsic::amdgcn_workitem_id_z, 0, 1024);
945-
946927
// amdgcn workgroup size
947928
case AMDGPU::BI__builtin_amdgcn_workgroup_size_x:
948929
return EmitAMDGPUWorkGroupSize(*this, 0);
@@ -964,12 +945,6 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
964945
case AMDGPU::BI__builtin_r600_recipsqrt_ieeef:
965946
return emitBuiltinWithOneOverloadedType<1>(*this, E,
966947
Intrinsic::r600_recipsqrt_ieee);
967-
case AMDGPU::BI__builtin_r600_read_tidig_x:
968-
return emitRangedBuiltin(*this, Intrinsic::r600_read_tidig_x, 0, 1024);
969-
case AMDGPU::BI__builtin_r600_read_tidig_y:
970-
return emitRangedBuiltin(*this, Intrinsic::r600_read_tidig_y, 0, 1024);
971-
case AMDGPU::BI__builtin_r600_read_tidig_z:
972-
return emitRangedBuiltin(*this, Intrinsic::r600_read_tidig_z, 0, 1024);
973948
case AMDGPU::BI__builtin_amdgcn_alignbit: {
974949
llvm::Value *Src0 = EmitScalarExpr(E->getArg(0));
975950
llvm::Value *Src1 = EmitScalarExpr(E->getArg(1));

‎clang/test/CodeGenOpenCL/builtins-amdgcn.cl‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -605,9 +605,9 @@ void test_s_getreg(volatile global uint *out)
605605
}
606606

607607
// CHECK-LABEL: @test_get_local_id(
608-
// CHECK: tail call noundef range(i32 0, 1024){{.*}} i32 @llvm.amdgcn.workitem.id.x()
609-
// CHECK: tail call noundef range(i32 0, 1024){{.*}} i32 @llvm.amdgcn.workitem.id.y()
610-
// CHECK: tail call noundef range(i32 0, 1024){{.*}} i32 @llvm.amdgcn.workitem.id.z()
608+
// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workitem.id.x()
609+
// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workitem.id.y()
610+
// CHECK: tail call{{.*}} i32 @llvm.amdgcn.workitem.id.z()
611611
void test_get_local_id(int d, global int *out)
612612
{
613613
switch (d) {
@@ -618,6 +618,10 @@ void test_get_local_id(int d, global int *out)
618618
}
619619
}
620620

621+
// CHECK: declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x()
622+
// CHECK: declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.y()
623+
// CHECK: declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.z()
624+
621625
// CHECK-LABEL: @test_get_workgroup_size(
622626
// CHECK: {{.*}}call align 8 dereferenceable(256){{.*}} ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
623627
// CHECK: getelementptr inbounds nuw i8, ptr addrspace(4) %{{.*}}, i64 12

‎clang/test/CodeGenOpenCL/builtins-r600.cl‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,9 @@ void test_get_group_id(int d, global int *out)
3939
}
4040

4141
// CHECK-LABEL: @test_get_local_id(
42-
// CHECK: tail call noundef range(i32 0, 1024) i32 @llvm.r600.read.tidig.x()
43-
// CHECK: tail call noundef range(i32 0, 1024) i32 @llvm.r600.read.tidig.y()
44-
// CHECK: tail call noundef range(i32 0, 1024) i32 @llvm.r600.read.tidig.z()
42+
// CHECK: tail call i32 @llvm.r600.read.tidig.x()
43+
// CHECK: tail call i32 @llvm.r600.read.tidig.y()
44+
// CHECK: tail call i32 @llvm.r600.read.tidig.z()
4545
void test_get_local_id(int d, global int *out)
4646
{
4747
switch (d) {
@@ -52,3 +52,6 @@ void test_get_local_id(int d, global int *out)
5252
}
5353
}
5454

55+
// CHECK: declare noundef range(i32 0, 1024) i32 @llvm.r600.read.tidig.x()
56+
// CHECK: declare noundef range(i32 0, 1024) i32 @llvm.r600.read.tidig.y()
57+
// CHECK: declare noundef range(i32 0, 1024) i32 @llvm.r600.read.tidig.z()

‎clang/test/Headers/gpuintrin.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -291,7 +291,7 @@ __gpu_kernel void foo() {
291291
// AMDGPU-NEXT: [[ENTRY:.*:]]
292292
// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
293293
// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
294-
// AMDGPU-NEXT: [[TMP0:%.*]] = call noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x()
294+
// AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
295295
// AMDGPU-NEXT: ret i32 [[TMP0]]
296296
//
297297
//
@@ -300,7 +300,7 @@ __gpu_kernel void foo() {
300300
// AMDGPU-NEXT: [[ENTRY:.*:]]
301301
// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
302302
// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
303-
// AMDGPU-NEXT: [[TMP0:%.*]] = call noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.y()
303+
// AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
304304
// AMDGPU-NEXT: ret i32 [[TMP0]]
305305
//
306306
//
@@ -309,7 +309,7 @@ __gpu_kernel void foo() {
309309
// AMDGPU-NEXT: [[ENTRY:.*:]]
310310
// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
311311
// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
312-
// AMDGPU-NEXT: [[TMP0:%.*]] = call noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.z()
312+
// AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
313313
// AMDGPU-NEXT: ret i32 [[TMP0]]
314314
//
315315
//

‎clang/test/Headers/gpuintrin_lang.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ __device__ int foo() { return __gpu_thread_id_x(); }
3636
// CUDA-LABEL: define dso_local i32 @foo(
3737
// CUDA-SAME: ) #[[ATTR0:[0-9]+]] {
3838
// CUDA-NEXT: [[ENTRY:.*:]]
39-
// CUDA-NEXT: [[TMP0:%.*]] = call {{.*}}i32 @llvm.nvvm.read.ptx.sreg.tid.x()
39+
// CUDA-NEXT: [[TMP0:%.*]] = call range(i32 0, 1024) i32 @llvm.nvvm.read.ptx.sreg.tid.x()
4040
// CUDA-NEXT: ret i32 [[TMP0]]
4141
//
4242
// HIP-LABEL: define dso_local i32 @foo(
@@ -46,29 +46,29 @@ __device__ int foo() { return __gpu_thread_id_x(); }
4646
// HIP-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
4747
// HIP-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
4848
// HIP-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
49-
// HIP-NEXT: [[TMP0:%.*]] = call noundef {{.*}}i32 @llvm.amdgcn.workitem.id.x()
49+
// HIP-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
5050
// HIP-NEXT: ret i32 [[TMP0]]
5151
//
5252
// OPENCL-LABEL: define dso_local i32 @foo(
5353
// OPENCL-SAME: ) #[[ATTR0:[0-9]+]] {
5454
// OPENCL-NEXT: [[ENTRY:.*:]]
55-
// OPENCL-NEXT: [[TMP0:%.*]] = call noundef {{.*}}i32 @llvm.amdgcn.workitem.id.x()
55+
// OPENCL-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
5656
// OPENCL-NEXT: ret i32 [[TMP0]]
5757
//
5858
// OPENMP-LABEL: define hidden i32 @foo(
5959
// OPENMP-SAME: ) #[[ATTR0:[0-9]+]] {
6060
// OPENMP-NEXT: [[ENTRY:.*:]]
61-
// OPENMP-NEXT: [[TMP0:%.*]] = call noundef {{.*}}i32 @llvm.amdgcn.workitem.id.x()
61+
// OPENMP-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
6262
// OPENMP-NEXT: ret i32 [[TMP0]]
6363
//
6464
// C89-LABEL: define dso_local i32 @foo(
65-
// C89-SAME: ) #[[ATTR2:[0-9]+]] {
65+
// C89-SAME: ) #[[ATTR0:[0-9]+]] {
6666
// C89-NEXT: [[ENTRY:.*:]]
6767
// C89-NEXT: [[RETVAL_I:%.*]] = alloca i32, align 4, addrspace(5)
6868
// C89-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
6969
// C89-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
7070
// C89-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
71-
// C89-NEXT: [[TMP0:%.*]] = call noundef {{.*}}i32 @llvm.amdgcn.workitem.id.x()
71+
// C89-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
7272
// C89-NEXT: ret i32 [[TMP0]]
7373
//
7474
int foo() { return __gpu_thread_id_x(); }

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

Lines changed: 31 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -20,11 +20,16 @@ def local_ptr_ty : LLVMQualPointerType<3>;
2020
// some preloaded register from a function that is known to not need it is a violation
2121
// of the calling convention and also program-level UB. Outside of such IR-level UB,
2222
// these preloaded registers are always set to a well-defined value and are thus `noundef`.
23-
class AMDGPUReadPreloadRegisterIntrinsic
24-
: DefaultAttrsIntrinsic<[llvm_i32_ty], [], [NoUndef<RetIndex>, IntrNoMem, IntrSpeculatable]>;
23+
class AMDGPUReadPreloadRegisterIntrinsic<
24+
list<IntrinsicProperty> ExtraAttrs = []>
25+
: DefaultAttrsIntrinsic<[llvm_i32_ty], [],
26+
!listconcat([NoUndef<RetIndex>, IntrNoMem,
27+
IntrSpeculatable],
28+
ExtraAttrs)>;
2529

26-
class AMDGPUReadPreloadRegisterIntrinsicNamed<string name>
27-
: DefaultAttrsIntrinsic<[llvm_i32_ty], [], [NoUndef<RetIndex>, IntrNoMem, IntrSpeculatable]>, ClangBuiltin<name>;
30+
class AMDGPUReadPreloadRegisterIntrinsicNamed<
31+
string name, list<IntrinsicProperty> ExtraAttrs = []>
32+
: AMDGPUReadPreloadRegisterIntrinsic<ExtraAttrs>, ClangBuiltin<name>;
2833

2934
// Used to tag image and resource intrinsics with information used to generate
3035
// mem operands.
@@ -35,17 +40,22 @@ class AMDGPURsrcIntrinsic<int rsrcarg, bit isimage = false> {
3540

3641
let TargetPrefix = "r600" in {
3742

38-
multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz {
39-
def _x : AMDGPUReadPreloadRegisterIntrinsic;
40-
def _y : AMDGPUReadPreloadRegisterIntrinsic;
41-
def _z : AMDGPUReadPreloadRegisterIntrinsic;
42-
}
43+
multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz<
44+
list<IntrinsicProperty> ExtraAttrs = []> {
45+
def _x : AMDGPUReadPreloadRegisterIntrinsic<ExtraAttrs>;
46+
def _y : AMDGPUReadPreloadRegisterIntrinsic<ExtraAttrs>;
47+
def _z : AMDGPUReadPreloadRegisterIntrinsic<ExtraAttrs>;
48+
}
4349

44-
multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<string prefix> {
45-
def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x")>;
46-
def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y")>;
47-
def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z")>;
48-
}
50+
multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<
51+
string prefix, list<IntrinsicProperty> ExtraAttrs = []> {
52+
def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x"),
53+
ExtraAttrs>;
54+
def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y"),
55+
ExtraAttrs>;
56+
def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z"),
57+
ExtraAttrs>;
58+
}
4959

5060
defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
5161
<"__builtin_r600_read_global_size">;
@@ -55,7 +65,9 @@ defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
5565
<"__builtin_r600_read_tgid">;
5666

5767
defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz;
58-
defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz;
68+
defm int_r600_read_tidig
69+
: AMDGPUReadPreloadRegisterIntrinsic_xyz_named<
70+
"__builtin_r600_read_tidig", [Range<RetIndex, 0, 1024>]>;
5971

6072
def int_r600_group_barrier : ClangBuiltin<"__builtin_r600_group_barrier">,
6173
Intrinsic<[], [], [IntrConvergent, IntrWillReturn]>;
@@ -146,7 +158,10 @@ let TargetPrefix = "amdgcn" in {
146158
// ABI Special Intrinsics
147159
//===----------------------------------------------------------------------===//
148160

149-
defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz;
161+
defm int_amdgcn_workitem_id
162+
: AMDGPUReadPreloadRegisterIntrinsic_xyz_named<
163+
"__builtin_amdgcn_workitem_id", [Range<RetIndex, 0, 1024>]>;
164+
150165
defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
151166
<"__builtin_amdgcn_workgroup_id">;
152167

‎llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ entry:
6161

6262
; GCN: define amdgpu_kernel void @test_inliner(
6363
; GCN-INL1: %c1 = tail call coldcc float @foo(
64-
; GCN-INLDEF: %cmp.i = fcmp ogt float %tmp2, 0.000000e+00
64+
; GCN-INLDEF: %cmp.i = fcmp ogt float %{{.+}}, 0.000000e+00
6565
; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c
6666
; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
6767
; GCN-MAXBB1: call coldcc void @foo_private_ptr

‎llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll‎

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -258,46 +258,41 @@ define amdgpu_kernel void @add_x_shl_max_offset() #1 {
258258
define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_alt() #1 {
259259
; CI-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
260260
; CI: ; %bb.0:
261-
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
262-
; CI-NEXT: v_xor_b32_e32 v0, 0xffff, v0
261+
; CI-NEXT: v_mul_i32_i24_e32 v0, -4, v0
263262
; CI-NEXT: v_mov_b32_e32 v1, 13
264263
; CI-NEXT: s_mov_b32 m0, -1
265-
; CI-NEXT: ds_write_b8 v0, v1
264+
; CI-NEXT: ds_write_b8 v0, v1 offset:65535
266265
; CI-NEXT: s_endpgm
267266
;
268267
; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
269268
; GFX9: ; %bb.0:
270-
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
271-
; GFX9-NEXT: v_xor_b32_e32 v0, 0xffff, v0
269+
; GFX9-NEXT: v_mul_i32_i24_e32 v0, -4, v0
272270
; GFX9-NEXT: v_mov_b32_e32 v1, 13
273-
; GFX9-NEXT: ds_write_b8 v0, v1
271+
; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535
274272
; GFX9-NEXT: s_endpgm
275273
;
276274
; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
277275
; GFX10: ; %bb.0:
278-
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
276+
; GFX10-NEXT: v_mul_i32_i24_e32 v0, -4, v0
279277
; GFX10-NEXT: v_mov_b32_e32 v1, 13
280-
; GFX10-NEXT: v_xor_b32_e32 v0, 0xffff, v0
281-
; GFX10-NEXT: ds_write_b8 v0, v1
278+
; GFX10-NEXT: ds_write_b8 v0, v1 offset:65535
282279
; GFX10-NEXT: s_endpgm
283280
;
284281
; GFX11-TRUE16-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
285282
; GFX11-TRUE16: ; %bb.0:
286283
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
287-
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
288-
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
289-
; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0xffff, v0
284+
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
285+
; GFX11-TRUE16-NEXT: v_mul_i32_i24_e32 v1, -4, v0
290286
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
291-
; GFX11-TRUE16-NEXT: ds_store_b8 v1, v0
287+
; GFX11-TRUE16-NEXT: ds_store_b8 v1, v0 offset:65535
292288
; GFX11-TRUE16-NEXT: s_endpgm
293289
;
294290
; GFX11-FAKE16-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
295291
; GFX11-FAKE16: ; %bb.0:
296292
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0
297-
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
298-
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
299-
; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, 0xffff, v0
300-
; GFX11-FAKE16-NEXT: ds_store_b8 v0, v1
293+
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
294+
; GFX11-FAKE16-NEXT: v_mul_i32_i24_e32 v0, -4, v0
295+
; GFX11-FAKE16-NEXT: ds_store_b8 v0, v1 offset:65535
301296
; GFX11-FAKE16-NEXT: s_endpgm
302297
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x()
303298
%.neg = mul i32 %x.i, -4
@@ -447,9 +442,9 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use() #1 {
447442
;
448443
; GFX11-LABEL: add_x_shl_neg_to_sub_multi_use:
449444
; GFX11: ; %bb.0:
450-
; GFX11-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_lshlrev_b32 v0, 2, v0
445+
; GFX11-NEXT: v_dual_mov_b32 v1, 13 :: v_dual_and_b32 v0, 0x3ff, v0
451446
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
452-
; GFX11-NEXT: v_and_b32_e32 v0, 0xffc, v0
447+
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
453448
; GFX11-NEXT: v_sub_nc_u32_e32 v0, 0, v0
454449
; GFX11-NEXT: ds_store_b32 v0, v1 offset:123
455450
; GFX11-NEXT: ds_store_b32 v0, v1 offset:456

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