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[SPARC][IAS] Add definitions for UA 2007 instructions
Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm#138401
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‎llvm/lib/Target/Sparc/Sparc.td‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,9 @@ def FeatureVIS3
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def FeatureUA2005
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: SubtargetFeature<"ua2005", "IsUA2005", "true",
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"Enable UltraSPARC Architecture 2005 extensions">;
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def FeatureUA2007
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: SubtargetFeature<"ua2007", "IsUA2007", "true",
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"Enable UltraSPARC Architecture 2007 extensions">;
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def FeatureLeon
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: SubtargetFeature<"leon", "IsLeon", "true",
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"Enable LEON extensions">;
@@ -160,10 +163,10 @@ def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2, FeatureUA2005]>;
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def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2, FeatureVIS3,
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FeatureUA2005]>;
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FeatureUA2005, FeatureUA2007]>;
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def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
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FeatureVIS, FeatureVIS2, FeatureVIS3,
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FeatureUA2005]>;
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FeatureUA2005, FeatureUA2007]>;
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// LEON 2 FT generic
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def : Processor<"leon2", LEON2Itineraries,

‎llvm/lib/Target/Sparc/SparcInstrFormats.td‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -260,6 +260,23 @@ multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
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itin>;
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}
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// 4-operand instructions.
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class F3_4<bits<6> op3val, bits<4> op5val, dag outs, dag ins,
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string asmstr, list<dag> pattern = [], InstrItinClass itin = NoItinerary>
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: F3<outs, ins, asmstr, pattern, itin> {
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bits<4> op5;
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bits<5> rs3;
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bits<5> rs2;
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let op = 2;
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let op3 = op3val;
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let op5 = op5val;
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let Inst{13-9} = rs3;
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let Inst{8-5} = op5;
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let Inst{4-0} = rs2;
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}
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class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin = NoItinerary>
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: InstSP<outs, ins, asmstr, pattern, itin> {

‎llvm/lib/Target/Sparc/SparcInstrInfo.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,10 @@ def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
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def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
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AssemblerPredicate<(all_of FeatureUA2005)>;
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// HasUA2007 - This is true when the target processor has UA 2007 extensions.
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def HasUA2007 : Predicate<"Subtarget->isUA2007()">,
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AssemblerPredicate<(all_of FeatureUA2007)>;
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// HasHardQuad - This is true when the target processor supports quad floating
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// point instructions.
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def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;

‎llvm/lib/Target/Sparc/SparcInstrUAOSA.td‎

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction formats, definitions and patterns needed for
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// UA 2005 instructions on SPARC.
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// UA 2005 and UA 2007 instructions on SPARC.
1111
//===----------------------------------------------------------------------===//
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class UA2005RegWin<string asmstr, bits<5> fcn>
@@ -17,6 +17,12 @@ class UA2005RegWin<string asmstr, bits<5> fcn>
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let rs2 = 0;
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}
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// Convenience template for 4-operand instructions
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class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val,
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RegisterClass RC>
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: F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
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!strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
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// UltraSPARC Architecture 2005 Instructions
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let Predicates = [HasUA2005] in {
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let hasSideEffects = 1 in {
@@ -26,3 +32,16 @@ def NORMALW : UA2005RegWin<"normalw", 0b00100>;
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def OTHERW : UA2005RegWin<"otherw", 0b00011>;
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}
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} // Predicates = [HasUA2005]
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// UltraSPARC Architecture 2007 Instructions
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let Predicates = [HasUA2007] in {
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def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
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def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
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def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
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def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
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def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
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def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
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def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
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def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
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} // Predicates = [HasUA2007]

‎llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt‎

Lines changed: 20 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s
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# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007 | FileCheck %s
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## UA 2005 instructions.
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@@ -10,3 +10,22 @@
1010
0x87,0x88,0x00,0x00
1111
# CHECK: normalw
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0x89,0x88,0x00,0x00
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## UA 2007 instructions.
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# CHECK: fmadds %f1, %f3, %f5, %f7
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0x8f,0xb8,0x4a,0x23
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# CHECK: fmaddd %f0, %f2, %f4, %f6
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0x8d,0xb8,0x08,0x42
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# CHECK: fmsubs %f1, %f3, %f5, %f7
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0x8f,0xb8,0x4a,0xa3
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# CHECK: fmsubd %f0, %f2, %f4, %f6
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0x8d,0xb8,0x08,0xc2
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# CHECK: fnmadds %f1, %f3, %f5, %f7
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0x8f,0xb8,0x4b,0xa3
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# CHECK: fnmaddd %f0, %f2, %f4, %f6
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0x8d,0xb8,0x09,0xc2
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# CHECK: fnmsubs %f1, %f3, %f5, %f7
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0x8f,0xb8,0x4b,0x23
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# CHECK: fnmsubd %f0, %f2, %f4, %f6
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0x8d,0xb8,0x09,0x42

‎llvm/test/MC/Sparc/sparc-ua2007.s‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
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! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2007 --implicit-check-not=error:
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! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2007 -show-encoding | FileCheck %s --check-prefixes=UA2007
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!! UA 2007 instructions.
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
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! UA2007: fmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0x23]
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fmadds %f1, %f3, %f5, %f7
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
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! UA2007: fmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0x42]
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fmaddd %f0, %f2, %f4, %f6
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
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! UA2007: fmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4a,0xa3]
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fmsubs %f1, %f3, %f5, %f7
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
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! UA2007: fmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x08,0xc2]
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fmsubd %f0, %f2, %f4, %f6
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
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! UA2007: fnmadds %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0xa3]
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fnmadds %f1, %f3, %f5, %f7
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
23+
! UA2007: fnmaddd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0xc2]
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fnmaddd %f0, %f2, %f4, %f6
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
26+
! UA2007: fnmsubs %f1, %f3, %f5, %f7 ! encoding: [0x8f,0xb8,0x4b,0x23]
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fnmsubs %f1, %f3, %f5, %f7
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! NO-UA2007: error: instruction requires a CPU feature not currently enabled
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! UA2007: fnmsubd %f0, %f2, %f4, %f6 ! encoding: [0x8d,0xb8,0x09,0x42]
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fnmsubd %f0, %f2, %f4, %f6

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