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[RISCV] Remove loads from single element fixed vector reduction tests. NFC (llvm#122808)
These tests weren't interested in the loads. Removing them reduces the diffs from llvm#122671.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll‎

Lines changed: 14 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -4,29 +4,25 @@
44

55
declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
66

7-
define half @vreduce_fadd_v1f16(ptr %x, half %s) {
7+
define half @vreduce_fadd_v1f16(<1 x half> %v, half %s) {
88
; CHECK-LABEL: vreduce_fadd_v1f16:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
11-
; CHECK-NEXT: vle16.v v8, (a0)
10+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
1211
; CHECK-NEXT: vfmv.f.s fa5, v8
1312
; CHECK-NEXT: fadd.h fa0, fa0, fa5
1413
; CHECK-NEXT: ret
15-
%v = load <1 x half>, ptr %x
1614
%red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
1715
ret half %red
1816
}
1917

20-
define half @vreduce_ord_fadd_v1f16(ptr %x, half %s) {
18+
define half @vreduce_ord_fadd_v1f16(<1 x half> %v, half %s) {
2119
; CHECK-LABEL: vreduce_ord_fadd_v1f16:
2220
; CHECK: # %bb.0:
2321
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
24-
; CHECK-NEXT: vle16.v v8, (a0)
2522
; CHECK-NEXT: vfmv.s.f v9, fa0
2623
; CHECK-NEXT: vfredosum.vs v8, v8, v9
2724
; CHECK-NEXT: vfmv.f.s fa0, v8
2825
; CHECK-NEXT: ret
29-
%v = load <1 x half>, ptr %x
3026
%red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
3127
ret half %red
3228
}
@@ -271,61 +267,53 @@ define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) {
271267

272268
declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
273269

274-
define float @vreduce_fadd_v1f32(ptr %x, float %s) {
270+
define float @vreduce_fadd_v1f32(<1 x float> %v, float %s) {
275271
; CHECK-LABEL: vreduce_fadd_v1f32:
276272
; CHECK: # %bb.0:
277-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
278-
; CHECK-NEXT: vle32.v v8, (a0)
273+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
279274
; CHECK-NEXT: vfmv.f.s fa5, v8
280275
; CHECK-NEXT: fadd.s fa0, fa0, fa5
281276
; CHECK-NEXT: ret
282-
%v = load <1 x float>, ptr %x
283277
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
284278
ret float %red
285279
}
286280

287-
define float @vreduce_ord_fadd_v1f32(ptr %x, float %s) {
281+
define float @vreduce_ord_fadd_v1f32(<1 x float> %v, float %s) {
288282
; CHECK-LABEL: vreduce_ord_fadd_v1f32:
289283
; CHECK: # %bb.0:
290284
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
291-
; CHECK-NEXT: vle32.v v8, (a0)
292285
; CHECK-NEXT: vfmv.s.f v9, fa0
293286
; CHECK-NEXT: vfredosum.vs v8, v8, v9
294287
; CHECK-NEXT: vfmv.f.s fa0, v8
295288
; CHECK-NEXT: ret
296-
%v = load <1 x float>, ptr %x
297289
%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
298290
ret float %red
299291
}
300292

301-
define float @vreduce_fwadd_v1f32(ptr %x, float %s) {
293+
define float @vreduce_fwadd_v1f32(<1 x half> %v, float %s) {
302294
; CHECK-LABEL: vreduce_fwadd_v1f32:
303295
; CHECK: # %bb.0:
304296
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
305-
; CHECK-NEXT: vle16.v v8, (a0)
306297
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
307298
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
308299
; CHECK-NEXT: vfmv.f.s fa5, v9
309300
; CHECK-NEXT: fadd.s fa0, fa0, fa5
310301
; CHECK-NEXT: ret
311-
%v = load <1 x half>, ptr %x
312302
%e = fpext <1 x half> %v to <1 x float>
313303
%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
314304
ret float %red
315305
}
316306

317-
define float @vreduce_ord_fwadd_v1f32(ptr %x, float %s) {
307+
define float @vreduce_ord_fwadd_v1f32(<1 x half> %v, float %s) {
318308
; CHECK-LABEL: vreduce_ord_fwadd_v1f32:
319309
; CHECK: # %bb.0:
320-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
321-
; CHECK-NEXT: vle16.v v8, (a0)
310+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
322311
; CHECK-NEXT: vfmv.s.f v9, fa0
323-
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
312+
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
324313
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
325314
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
326315
; CHECK-NEXT: vfmv.f.s fa0, v8
327316
; CHECK-NEXT: ret
328-
%v = load <1 x half>, ptr %x
329317
%e = fpext <1 x half> %v to <1 x float>
330318
%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
331319
ret float %red
@@ -815,61 +803,53 @@ define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
815803

816804
declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>)
817805

818-
define double @vreduce_fadd_v1f64(ptr %x, double %s) {
806+
define double @vreduce_fadd_v1f64(<1 x double> %v, double %s) {
819807
; CHECK-LABEL: vreduce_fadd_v1f64:
820808
; CHECK: # %bb.0:
821809
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
822-
; CHECK-NEXT: vle64.v v8, (a0)
823810
; CHECK-NEXT: vfmv.f.s fa5, v8
824811
; CHECK-NEXT: fadd.d fa0, fa0, fa5
825812
; CHECK-NEXT: ret
826-
%v = load <1 x double>, ptr %x
827813
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
828814
ret double %red
829815
}
830816

831-
define double @vreduce_ord_fadd_v1f64(ptr %x, double %s) {
817+
define double @vreduce_ord_fadd_v1f64(<1 x double> %v, double %s) {
832818
; CHECK-LABEL: vreduce_ord_fadd_v1f64:
833819
; CHECK: # %bb.0:
834820
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
835-
; CHECK-NEXT: vle64.v v8, (a0)
836821
; CHECK-NEXT: vfmv.s.f v9, fa0
837822
; CHECK-NEXT: vfredosum.vs v8, v8, v9
838823
; CHECK-NEXT: vfmv.f.s fa0, v8
839824
; CHECK-NEXT: ret
840-
%v = load <1 x double>, ptr %x
841825
%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
842826
ret double %red
843827
}
844828

845-
define double @vreduce_fwadd_v1f64(ptr %x, double %s) {
829+
define double @vreduce_fwadd_v1f64(<1 x float> %v, double %s) {
846830
; CHECK-LABEL: vreduce_fwadd_v1f64:
847831
; CHECK: # %bb.0:
848832
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
849-
; CHECK-NEXT: vle32.v v8, (a0)
850833
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
851834
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
852835
; CHECK-NEXT: vfmv.f.s fa5, v9
853836
; CHECK-NEXT: fadd.d fa0, fa0, fa5
854837
; CHECK-NEXT: ret
855-
%v = load <1 x float>, ptr %x
856838
%e = fpext <1 x float> %v to <1 x double>
857839
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
858840
ret double %red
859841
}
860842

861-
define double @vreduce_ord_fwadd_v1f64(ptr %x, double %s) {
843+
define double @vreduce_ord_fwadd_v1f64(<1 x float> %v, double %s) {
862844
; CHECK-LABEL: vreduce_ord_fwadd_v1f64:
863845
; CHECK: # %bb.0:
864846
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
865-
; CHECK-NEXT: vle32.v v8, (a0)
866847
; CHECK-NEXT: vfmv.s.f v9, fa0
867848
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
868849
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
869850
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
870851
; CHECK-NEXT: vfmv.f.s fa0, v8
871852
; CHECK-NEXT: ret
872-
%v = load <1 x float>, ptr %x
873853
%e = fpext <1 x float> %v to <1 x double>
874854
%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
875855
ret double %red

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