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[SPARC][MC] Add tests for VIS family instructions
Also fix up any mistakes/typos in instruction definitions. Reviewers: rorth, s-barannikov, brad0, MaskRay Reviewed By: s-barannikov Pull Request: llvm#130967
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‎llvm/lib/Target/Sparc/SparcInstrFormats.td‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,21 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
201201
let Inst{4-0} = rs2;
202202
}
203203

204+
// SIAM instruction
205+
class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
206+
string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
207+
: F3<outs, ins, asmstr, pattern, itin> {
208+
bits<3> mode;
209+
210+
let op = opVal;
211+
let op3 = op3val;
212+
let rd = 0;
213+
let rs1 = 0;
214+
let Inst{13-5} = opfval; // fp opcode
215+
let Inst{4-3} = 0;
216+
let Inst{2-0} = mode;
217+
}
218+
204219
// Shift by register rs2.
205220
class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
206221
string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>

‎llvm/lib/Target/Sparc/SparcInstrInfo.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,9 @@ def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
8282
// Instruction Pattern Stuff
8383
//===----------------------------------------------------------------------===//
8484

85+
// FIXME these should have AsmOperandClass.
86+
def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>;
87+
8588
def simm10 : PatLeaf<(imm), [{ return isInt<10>(N->getSExtValue()); }]>;
8689

8790
def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;

‎llvm/lib/Target/Sparc/SparcInstrVIS.td‎

Lines changed: 65 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -7,76 +7,91 @@
77
//===----------------------------------------------------------------------===//
88
//
99
// This file contains instruction formats, definitions and patterns needed for
10-
// VIS, VIS II, VIS II instructions on SPARC.
10+
// VIS, VIS II, VIS III instructions on SPARC.
1111
//===----------------------------------------------------------------------===//
1212

1313
// VIS Instruction Format.
14-
class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
15-
list<dag> pattern>
16-
: F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
14+
class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr>
15+
: F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, []>;
1716

1817
class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
1918
: VISInstFormat<opfval,
2019
(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
21-
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
20+
!strconcat(OpcStr, " $rs1, $rs2, $rd")>;
2221

2322
// VIS Instruction with integer destination register.
2423
class VISInstID<bits<9> opfval, string OpcStr>
2524
: VISInstFormat<opfval,
2625
(outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
27-
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
26+
!strconcat(OpcStr, " $rs1, $rs2, $rd")>;
2827

2928
// For VIS Instructions with no operand.
3029
let rd = 0, rs1 = 0, rs2 = 0 in
3130
class VISInst0<bits<9> opfval, string asmstr>
32-
: VISInstFormat<opfval, (outs), (ins), asmstr, []>;
31+
: VISInstFormat<opfval, (outs), (ins), asmstr>;
3332

3433
// For VIS Instructions with only rs1, rd operands.
3534
let rs2 = 0 in
3635
class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
3736
: VISInstFormat<opfval,
3837
(outs RC:$rd), (ins RC:$rs1),
39-
!strconcat(OpcStr, " $rs1, $rd"), []>;
38+
!strconcat(OpcStr, " $rs1, $rd")>;
4039

4140
// For VIS Instructions with only rs2, rd operands.
4241
let rs1 = 0 in
4342
class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
4443
: VISInstFormat<opfval,
4544
(outs RC:$rd), (ins RC:$rs2),
46-
!strconcat(OpcStr, " $rs2, $rd"), []>;
45+
!strconcat(OpcStr, " $rs2, $rd")>;
4746

4847
// For VIS Instructions with only rd operand.
4948
let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
5049
class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
5150
: VISInstFormat<opfval,
5251
(outs RC:$rd), (ins RC:$f),
53-
!strconcat(OpcStr, " $rd"), []>;
52+
!strconcat(OpcStr, " $rd")>;
5453

5554
// VIS 1 Instructions
5655
let Predicates = [HasVIS] in {
5756

5857
def FPADD16 : VISInst<0b001010000, "fpadd16">;
59-
def FPADD16S : VISInst<0b001010001, "fpadd16s">;
58+
def FPADD16S : VISInst<0b001010001, "fpadd16s", FPRegs>;
6059
def FPADD32 : VISInst<0b001010010, "fpadd32">;
61-
def FPADD32S : VISInst<0b001010011, "fpadd32s">;
60+
def FPADD32S : VISInst<0b001010011, "fpadd32s", FPRegs>;
6261
def FPSUB16 : VISInst<0b001010100, "fpsub16">;
63-
def FPSUB16S : VISInst<0b001010101, "fpsub16S">;
62+
def FPSUB16S : VISInst<0b001010101, "fpsub16s", FPRegs>;
6463
def FPSUB32 : VISInst<0b001010110, "fpsub32">;
65-
def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
64+
def FPSUB32S : VISInst<0b001010111, "fpsub32s", FPRegs>;
6665

6766
def FPACK16 : VISInst2<0b000111011, "fpack16">;
6867
def FPACK32 : VISInst <0b000111010, "fpack32">;
69-
def FPACKFIX : VISInst2<0b000111101, "fpackfix">;
70-
def FEXPAND : VISInst2<0b001001101, "fexpand">;
71-
def FPMERGE : VISInst <0b001001011, "fpmerge">;
72-
73-
def FMUL8X16 : VISInst<0b000110001, "fmul8x16">;
74-
def FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">;
75-
def FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">;
68+
let rs1 = 0 in
69+
def FPACKFIX : VISInstFormat<0b000111101,
70+
(outs FPRegs:$rd), (ins DFPRegs:$rs2), "fpackfix $rs2, $rd">;
71+
let rs1 = 0 in
72+
def FEXPAND : VISInstFormat<0b001001101,
73+
(outs DFPRegs:$rd), (ins FPRegs:$rs2), "fexpand $rs2, $rd">;
74+
def FPMERGE : VISInstFormat<0b001001011,
75+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
76+
"fpmerge $rs1, $rs2, $rd">;
77+
78+
def FMUL8X16 : VISInstFormat<0b000110001,
79+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, DFPRegs:$rs2),
80+
"fmul8x16 $rs1, $rs2, $rd">;
81+
def FMUL8X16AU : VISInstFormat<0b000110011,
82+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
83+
"fmul8x16au $rs1, $rs2, $rd">;
84+
def FMUL8X16AL : VISInstFormat<0b000110101,
85+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
86+
"fmul8x16al $rs1, $rs2, $rd">;
7687
def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">;
7788
def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">;
78-
def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">;
79-
def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">;
89+
def FMULD8SUX16 : VISInstFormat<0b000111000,
90+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
91+
"fmuld8sux16 $rs1, $rs2, $rd">;
92+
def FMULD8ULX16 : VISInstFormat<0b000111001,
93+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
94+
"fmuld8ulx16 $rs1, $rs2, $rd">;
8095

8196
def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
8297
def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
@@ -148,9 +163,11 @@ def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
148163
let Predicates = [HasVIS2] in {
149164

150165
def BMASK : VISInst<0b000011001, "bmask", I64Regs>;
151-
def BSHUFFLE : VISInst<0b000011100, "bshuffle">;
166+
def BSHUFFLE : VISInst<0b001001100, "bshuffle">;
152167

153-
def SIAM : VISInst0<0b010000001, "siam">;
168+
let rd = 0, rs1 = 0 in
169+
def SIAM : F3_3_siam<0b10, 0b110110, 0b010000001, (outs),
170+
(ins i32imm:$mode), "siam $mode", []>;
154171

155172
def EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>;
156173
def EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>;
@@ -172,59 +189,59 @@ def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
172189

173190
let rd = 0, rs1 = 0 in {
174191
def CMASK8 : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
175-
"cmask8 $rs2", []>;
192+
"cmask8 $rs2">;
176193
def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
177-
"cmask16 $rs2", []>;
194+
"cmask16 $rs2">;
178195
def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
179-
"cmask32 $rs2", []>;
196+
"cmask32 $rs2">;
180197

181198
}
182199

183200
def FCHKSM16 : VISInst<0b001000100, "fchksm16">;
184201

185202
def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
186-
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
203+
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
187204
"fhadds $rs1, $rs2, $rd", []>;
188205
def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
189206
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
190207
"fhaddd $rs1, $rs2, $rd", []>;
191208
def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
192-
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
209+
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
193210
"fhsubs $rs1, $rs2, $rd", []>;
194211
def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
195212
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
196213
"fhsubd $rs1, $rs2, $rd", []>;
197214
def FLCMPS : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
198-
(ins DFPRegs:$rs1, DFPRegs:$rs2),
199-
"flcmps $rd, $rs1, $rs2", []>;
215+
(ins FPRegs:$rs1, FPRegs:$rs2),
216+
"flcmps $rd, $rs1, $rs2">;
200217
def FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
201218
(ins DFPRegs:$rs1, DFPRegs:$rs2),
202-
"flcmpd $rd, $rs1, $rs2", []>;
219+
"flcmpd $rd, $rs1, $rs2">;
203220

204221
def FMEAN16 : VISInst<0b001000000, "fmean16">;
205222

206223
def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
207-
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
224+
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
208225
"fnadds $rs1, $rs2, $rd", []>;
209226
def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
210227
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
211228
"fnaddd $rs1, $rs2, $rd", []>;
212229
def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
213-
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
230+
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
214231
"fnhadds $rs1, $rs2, $rd", []>;
215232
def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
216233
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
217234
"fnhaddd $rs1, $rs2, $rd", []>;
218235

219236
def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
220-
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
221-
"fnhadds $rs1, $rs2, $rd", []>;
237+
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
238+
"fnmuls $rs1, $rs2, $rd", []>;
222239
def FNMULD : F3_3<0b10, 0b110100, 0b001011010,
223240
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
224-
"fnhaddd $rs1, $rs2, $rd", []>;
241+
"fnmuld $rs1, $rs2, $rd", []>;
225242
def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
226-
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
227-
"fnhadds $rs1, $rs2, $rd", []>;
243+
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
244+
"fnsmuld $rs1, $rs2, $rd", []>;
228245

229246
def FPADD64 : VISInst<0b001000010, "fpadd64">;
230247

@@ -239,24 +256,24 @@ def FSRA32 : VISInst<0b000101111, "fsra32">;
239256

240257
let rs1 = 0 in
241258
def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
242-
(ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
259+
(ins I64Regs:$rs2), "lzcnt $rs2, $rd">;
243260

244261
let rs1 = 0 in {
245262
def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
246-
(ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;
263+
(ins DFPRegs:$rs2), "movstosw $rs2, $rd">;
247264
def MOVSTOUW : VISInstFormat<0b100010001, (outs I64Regs:$rd),
248-
(ins DFPRegs:$rs2), "movstouw $rs2, $rd", []>;
265+
(ins DFPRegs:$rs2), "movstouw $rs2, $rd">;
249266
def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
250-
(ins DFPRegs:$rs2), "movdtox $rs2, $rd", []>;
267+
(ins DFPRegs:$rs2), "movdtox $rs2, $rd">;
251268
def MOVWTOS : VISInstFormat<0b100011001, (outs DFPRegs:$rd),
252-
(ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
269+
(ins I64Regs:$rs2), "movwtos $rs2, $rd">;
253270
def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
254-
(ins I64Regs:$rs2), "movdtox $rs2, $rd", []>;
271+
(ins I64Regs:$rs2), "movxtod $rs2, $rd">;
255272
}
256273

257-
def PDISTN : VISInst<0b000111111, "pdistn">;
274+
def PDISTN : VISInstID<0b000111111, "pdistn">;
258275

259276
def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
260277
def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
261-
def XMULXHI : VISInst<0b100010111, "xmulxhi", I64Regs>;
278+
def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
262279
} // Predicates = [IsVIS3]

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