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#include "qemu/module.h"
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#include "target/arm/arm-powerctl.h"
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#include "hw/core/cpu.h"
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-
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- #ifndef DEBUG_IMX6_SRC
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- #define DEBUG_IMX6_SRC 0
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- #endif
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-
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- #define DPRINTF (fmt , args ...) \
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- do { \
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- if (DEBUG_IMX6_SRC) { \
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- fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX6_SRC, \
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- __func__, ##args); \
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- } \
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- } while (0)
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+ #include "trace.h"
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static const char * imx6_src_reg_name (uint32_t reg )
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{
@@ -87,7 +76,7 @@ static void imx6_src_reset(DeviceState *dev)
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{
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IMX6SRCState * s = IMX6_SRC (dev );
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- DPRINTF ( "\n" );
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+ trace_imx6_src_reset ( );
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memset (s -> regs , 0 , sizeof (s -> regs ));
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@@ -111,7 +100,7 @@ static uint64_t imx6_src_read(void *opaque, hwaddr offset, unsigned size)
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}
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- DPRINTF ( "reg[%s] => 0x%" PRIx32 "\n" , imx6_src_reg_name (index ), value );
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+ trace_imx6_src_read ( imx6_src_reg_name (index ), value );
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return value ;
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}
@@ -134,8 +123,7 @@ static void imx6_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
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assert (bql_locked ());
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s -> regs [SRC_SCR ] = deposit32 (s -> regs [SRC_SCR ], ri -> reset_bit , 1 , 0 );
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- DPRINTF ("reg[%s] <= 0x%" PRIx32 "\n" ,
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- imx6_src_reg_name (SRC_SCR ), s -> regs [SRC_SCR ]);
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+ trace_imx6_clear_reset_bit (imx6_src_reg_name (SRC_SCR ), s -> regs [SRC_SCR ]);
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g_free (ri );
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}
@@ -173,8 +161,7 @@ static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value,
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return ;
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}
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- DPRINTF ("reg[%s] <= 0x%" PRIx32 "\n" , imx6_src_reg_name (index ),
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- (uint32_t )current_value );
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+ trace_imx6_src_write (imx6_src_reg_name (index ), value );
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change_mask = s -> regs [index ] ^ (uint32_t )current_value ;
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