Skip to content

Commit 3dc7e1d

Browse files
committed
tcg/sparc64: Use SRA, SRL for {s}extract_i64
Extracts which abut bit 32 may use 32-bit shifts. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
1 parent 42103c4 commit 3dc7e1d

File tree

2 files changed

+20
-4
lines changed

2 files changed

+20
-4
lines changed

tcg/sparc64/tcg-target-has.h

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,8 @@ extern bool use_vis3_instructions;
3333
#define TCG_TARGET_HAS_ctz_i32 0
3434
#define TCG_TARGET_HAS_ctpop_i32 0
3535
#define TCG_TARGET_HAS_deposit_i32 0
36-
#define TCG_TARGET_HAS_extract_i32 0
37-
#define TCG_TARGET_HAS_sextract_i32 0
36+
#define TCG_TARGET_HAS_extract_i32 1
37+
#define TCG_TARGET_HAS_sextract_i32 1
3838
#define TCG_TARGET_HAS_extract2_i32 0
3939
#define TCG_TARGET_HAS_negsetcond_i32 1
4040
#define TCG_TARGET_HAS_add2_i32 1
@@ -68,8 +68,8 @@ extern bool use_vis3_instructions;
6868
#define TCG_TARGET_HAS_ctz_i64 0
6969
#define TCG_TARGET_HAS_ctpop_i64 0
7070
#define TCG_TARGET_HAS_deposit_i64 0
71-
#define TCG_TARGET_HAS_extract_i64 0
72-
#define TCG_TARGET_HAS_sextract_i64 0
71+
#define TCG_TARGET_HAS_extract_i64 1
72+
#define TCG_TARGET_HAS_sextract_i64 1
7373
#define TCG_TARGET_HAS_extract2_i64 0
7474
#define TCG_TARGET_HAS_negsetcond_i64 1
7575
#define TCG_TARGET_HAS_add2_i64 1
@@ -83,4 +83,9 @@ extern bool use_vis3_instructions;
8383

8484
#define TCG_TARGET_HAS_tst 1
8585

86+
#define TCG_TARGET_extract_valid(type, ofs, len) \
87+
((type) == TCG_TYPE_I64 && (ofs) + (len) == 32)
88+
89+
#define TCG_TARGET_sextract_valid TCG_TARGET_extract_valid
90+
8691
#endif

tcg/sparc64/tcg-target.c.inc

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1510,6 +1510,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
15101510
tcg_out_mb(s, a0);
15111511
break;
15121512

1513+
case INDEX_op_extract_i64:
1514+
tcg_debug_assert(a2 + args[3] == 32);
1515+
tcg_out_arithi(s, a0, a1, a2, SHIFT_SRL);
1516+
break;
1517+
case INDEX_op_sextract_i64:
1518+
tcg_debug_assert(a2 + args[3] == 32);
1519+
tcg_out_arithi(s, a0, a1, a2, SHIFT_SRA);
1520+
break;
1521+
15131522
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
15141523
case INDEX_op_mov_i64:
15151524
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -1559,6 +1568,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
15591568
case INDEX_op_ext32u_i64:
15601569
case INDEX_op_ext_i32_i64:
15611570
case INDEX_op_extu_i32_i64:
1571+
case INDEX_op_extract_i64:
1572+
case INDEX_op_sextract_i64:
15621573
case INDEX_op_qemu_ld_a32_i32:
15631574
case INDEX_op_qemu_ld_a64_i32:
15641575
case INDEX_op_qemu_ld_a32_i64:

0 commit comments

Comments
 (0)