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#include "qemu/log.h"
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#include "qemu/module.h"
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- #ifndef STM_USART_ERR_DEBUG
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- #define STM_USART_ERR_DEBUG 0
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- #endif
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-
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- #define DB_PRINT_L (lvl , fmt , args ...) do { \
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- if (STM_USART_ERR_DEBUG >= lvl) { \
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- qemu_log("%s: " fmt, __func__, ## args); \
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- } \
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- } while (0)
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-
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- #define DB_PRINT (fmt , args ...) DB_PRINT_L(1, fmt, ## args)
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+ #include "trace.h"
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static int stm32f2xx_usart_can_receive (void * opaque )
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{
@@ -67,10 +57,11 @@ static void stm32f2xx_update_irq(STM32F2XXUsartState *s)
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static void stm32f2xx_usart_receive (void * opaque , const uint8_t * buf , int size )
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{
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STM32F2XXUsartState * s = opaque ;
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+ DeviceState * d = DEVICE (s );
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if (!(s -> usart_cr1 & USART_CR1_UE && s -> usart_cr1 & USART_CR1_RE )) {
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/* USART not enabled - drop the chars */
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- DB_PRINT ( "Dropping the chars\n" );
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+ trace_stm32f2xx_usart_drop ( d -> id );
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return ;
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}
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@@ -79,7 +70,7 @@ static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
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stm32f2xx_update_irq (s );
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- DB_PRINT ( "Receiving: %c\n" , s -> usart_dr );
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+ trace_stm32f2xx_usart_receive ( d -> id , * buf );
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}
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static void stm32f2xx_usart_reset (DeviceState * dev )
@@ -101,49 +92,55 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
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unsigned int size )
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{
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STM32F2XXUsartState * s = opaque ;
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- uint64_t retvalue ;
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-
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- DB_PRINT ("Read 0x%" HWADDR_PRIx "\n" , addr );
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+ DeviceState * d = DEVICE (s );
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+ uint64_t retvalue = 0 ;
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switch (addr ) {
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case USART_SR :
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retvalue = s -> usart_sr ;
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qemu_chr_fe_accept_input (& s -> chr );
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- return retvalue ;
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+ break ;
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case USART_DR :
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- DB_PRINT ("Value: 0x%" PRIx32 ", %c\n" , s -> usart_dr , (char ) s -> usart_dr );
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retvalue = s -> usart_dr & 0x3FF ;
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s -> usart_sr &= ~USART_SR_RXNE ;
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qemu_chr_fe_accept_input (& s -> chr );
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stm32f2xx_update_irq (s );
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- return retvalue ;
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+ break ;
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case USART_BRR :
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- return s -> usart_brr ;
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+ retvalue = s -> usart_brr ;
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+ break ;
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case USART_CR1 :
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- return s -> usart_cr1 ;
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+ retvalue = s -> usart_cr1 ;
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+ break ;
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case USART_CR2 :
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- return s -> usart_cr2 ;
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+ retvalue = s -> usart_cr2 ;
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+ break ;
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case USART_CR3 :
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- return s -> usart_cr3 ;
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+ retvalue = s -> usart_cr3 ;
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+ break ;
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case USART_GTPR :
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- return s -> usart_gtpr ;
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+ retvalue = s -> usart_gtpr ;
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+ break ;
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default :
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qemu_log_mask (LOG_GUEST_ERROR ,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n" , __func__ , addr );
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return 0 ;
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}
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- return 0 ;
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+ trace_stm32f2xx_usart_read (d -> id , size , addr , retvalue );
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+
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+ return retvalue ;
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}
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static void stm32f2xx_usart_write (void * opaque , hwaddr addr ,
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uint64_t val64 , unsigned int size )
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{
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STM32F2XXUsartState * s = opaque ;
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+ DeviceState * d = DEVICE (s );
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uint32_t value = val64 ;
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unsigned char ch ;
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- DB_PRINT ( "Write 0x%" PRIx32 ", 0x%" HWADDR_PRIx "\n" , value , addr );
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+ trace_stm32f2xx_usart_write ( d -> id , size , addr , val64 );
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switch (addr ) {
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case USART_SR :
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