cpu: add basic support for some 65C02 opcodes

This is very much a RFC rather than something which is finished and proposed for
merging. I've got my own 6502 homebrew project at https://github.com/rjw57/buri
and I make use of the 65C02 instructions such as PHX, PHY, etc.

This commit adds just enough support to boot the 65C02 ROM image I have. This is
a work-in-progress change and is not complete 65C02 support by any means.

My question is: is this worth pursuing further? Would you be interested in 65C02
support? If so, would you want some form of configuration allowing 65C02-support
to be switched on/off?

Author: rjw57

cpu/cpu.go

@@ -156,8 +156,15 @@ func (c *Cpu) memoryAddress(in Instruction) uint16 {
 		return uint16(in.Op8 + c.X)
 	case zeropageY:
 		return uint16(in.Op8 + c.Y)
+
+	// 65C02-only modes
+	case zpindirect:
+		return c.Bus.Read16(uint16(in.Op8))
+	case indirect:
+		return c.Bus.Read16(uint16(in.Op16))
+
 	default:
-		panic("unhandled addressing")
+		panic(fmt.Sprintf("unhandled addressing: %v", in.addressing))
 	}
 }
 
@@ -304,6 +311,18 @@ func (c *Cpu) execute(in Instruction) {
 		c.TXS(in)
 	case tya:
 		c.TYA(in)
+	case phx:
+		c.PHX(in)
+	case phy:
+		c.PHY(in)
+	case plx:
+		c.PLX(in)
+	case ply:
+		c.PLY(in)
+	case stz:
+		c.STZ(in)
+	case bra:
+		c.BRA(in)
 	case _end:
 		c._END(in)
 	default:
@@ -392,6 +411,11 @@ func (c *Cpu) BPL(in Instruction) {
 	}
 }
 
+// BRA: Unconditional branch
+func (c *Cpu) BRA(in Instruction) {
+	c.branch(in)
+}
+
 // BRK: software interrupt
 func (c *Cpu) BRK(in Instruction) {
 	// temporarily used to dump status
@@ -550,6 +574,30 @@ func (c *Cpu) PLA(in Instruction) {
 	c.AC = c.Bus.Read(0x0100 + uint16(c.SP))
 }
 
+// PHX: Push X onto stack.
+func (c *Cpu) PHX(in Instruction) {
+	c.Bus.Write(0x0100+uint16(c.SP), c.X)
+	c.SP--
+}
+
+// PLX: Pull X from stack.
+func (c *Cpu) PLX(in Instruction) {
+	c.SP++
+	c.X = c.Bus.Read(0x0100 + uint16(c.SP))
+}
+
+// PHY: Push Y onto stack.
+func (c *Cpu) PHY(in Instruction) {
+	c.Bus.Write(0x0100+uint16(c.SP), c.Y)
+	c.SP--
+}
+
+// PLY: Pull Y from stack.
+func (c *Cpu) PLY(in Instruction) {
+	c.SP++
+	c.Y = c.Bus.Read(0x0100 + uint16(c.SP))
+}
+
 // ROL: Rotate memory or accumulator left one bit.
 func (c *Cpu) ROL(in Instruction) {
 	carry := c.getStatusInt(sCarry)
@@ -637,6 +685,11 @@ func (c *Cpu) STY(in Instruction) {
 	c.Bus.Write(c.memoryAddress(in), c.Y)
 }
 
+// STZ: Store zero to memory.
+func (c *Cpu) STZ(in Instruction) {
+	c.Bus.Write(c.memoryAddress(in), 0)
+}
+
 // TAX: Transfer accumulator to index register X.
 func (c *Cpu) TAX(in Instruction) {
 	c.X = c.AC

cpu/op_type.go

@@ -18,6 +18,9 @@ const (
 	zeropage
 	zeropageX
 	zeropageY
+
+	// 65C02 only
+	zpindirect
 )
 
 var addressingNames = [...]string{
@@ -35,6 +38,7 @@ var addressingNames = [...]string{
 	"zeropage",
 	"zeropageX",
 	"zeropageY",
+	"(zeropage)",
 }
 
 // adc..tya represent the 6502 instruction set mnemonics. Each mnemonic maps to
@@ -97,6 +101,17 @@ const (
 	txa
 	txs
 	tya
+
+	// 65{S}C02-only
+	bra
+	phx
+	phy
+	plx
+	ply
+	stz
+	trb
+	tsb
+
 	_end
 )
 
@@ -158,6 +173,17 @@ var instructionNames = [...]string{
 	"TXA",
 	"TXS",
 	"TYA",
+
+	// 65{S}C02-only
+	"BRA",
+	"PHX",
+	"PHY",
+	"PLX",
+	"PLY",
+	"STZ",
+	"TRB",
+	"TSB",
+
 	"_END",
 }
 
@@ -351,5 +377,29 @@ var optypes = map[uint8]OpType{
 	0x8A: OpType{0x8A, txa, implied, 1, 2},
 	0x9A: OpType{0x9A, txs, implied, 1, 2},
 	0x98: OpType{0x98, tya, implied, 1, 2},
+
+	// 65{S}C02 only
+	0x80: OpType{0x80, bra, relative, 2, 3},
+	0xDA: OpType{0xDA, phx, implied, 1, 3},
+	0x5A: OpType{0x5A, phy, implied, 1, 3},
+	0xFA: OpType{0xFA, plx, implied, 1, 4},
+	0x7A: OpType{0x7A, ply, implied, 1, 4},
+	0x64: OpType{0x64, stz, zeropage, 2, 3},
+	0x74: OpType{0x74, stz, zeropageX, 2, 4},
+	0x9C: OpType{0x9C, stz, absolute, 3, 4},
+	0x9E: OpType{0x9E, stz, absoluteX, 3, 5},
+	0x14: OpType{0x14, trb, zeropage, 2, 5},
+	0x1C: OpType{0x1C, trb, absolute, 3, 6},
+	0x04: OpType{0x04, tsb, zeropage, 2, 5},
+	0x0C: OpType{0x0C, tsb, absolute, 3, 5},
+	0x12: OpType{0x12, ora, zpindirect, 2, 5},
+	0x32: OpType{0x32, and, zpindirect, 2, 5},
+	0x52: OpType{0x52, eor, zpindirect, 2, 5},
+	0x72: OpType{0x72, adc, zpindirect, 2, 5},
+	0x92: OpType{0x92, sta, zpindirect, 2, 5},
+	0xB2: OpType{0xB2, lda, zpindirect, 2, 5},
+	0xD2: OpType{0xD2, cmp, zpindirect, 2, 5},
+	0xF2: OpType{0xF2, sbc, zpindirect, 2, 5},
+
 	0xFF: OpType{0xFF, _end, implied, 1, 1},
 }