Fix clang build

Author: peadar

aarch64.cc

@@ -119,7 +119,7 @@ void opReg(Regs &regs, Op op, int reg, Value &value) {
          break;
 
       case 64 ...  95: {
-         auto &simd = *reinterpret_cast< typename Op::Reg<Simd128> *>(&regs.fpsimd.vregs[reg-64]);
+         auto &simd = *reinterpret_cast< typename Op::template Reg<Simd128> *>(&regs.fpsimd.vregs[reg-64]);
          regop(op, simd, value);
          break;
       }

i386.cc

@@ -119,13 +119,13 @@ void opReg(Regs &regs, Op op, int reg, Value &value) {
          break;
 
       case 11 ... 18: {
-         auto &st = *reinterpret_cast< typename Op::Reg<i387Float> *> (regs.fpx.st_space + (reg-11) * 4);
+         auto &st = *reinterpret_cast< typename Op::template Reg<i387Float> *> (regs.fpx.st_space + (reg-11) * 4);
          regop(op, st, value);
          break;
       }
 
       case 21 ... 28: {
-         auto &st = *reinterpret_cast< typename Op::Reg<Simd128> *> (regs.fpx.xmm_space + (reg-21) * 4);
+         auto &st = *reinterpret_cast< typename Op::template Reg<Simd128> *> (regs.fpx.xmm_space + (reg-21) * 4);
          regop(op, st, value);
          break;
       }

x86_64.cc

@@ -155,19 +155,19 @@ void opReg(Regs &regs, Op op, int reg, Value &value) {
          regop(op, regs.user.rip, value);
          break;
       case 17 ... 32: {
-         auto &xmm = *reinterpret_cast< typename Op::Reg<Simd128> *> (regs.fp.xmm_space + (reg-17) * 4);
+         auto &xmm = *reinterpret_cast< typename Op::template Reg<Simd128> *> (regs.fp.xmm_space + (reg-17) * 4);
          regop(op, xmm, value);
          break;
       }
       case 33 ... 40: {
-         auto &st = *reinterpret_cast< typename Op::Reg<i387Float> *> (regs.fp.st_space + (reg-33) * 4);
+         auto &st = *reinterpret_cast< typename Op::template Reg<i387Float> *> (regs.fp.st_space + (reg-33) * 4);
          regop(op, st, value);
          break;
       }
       case 41 ... 48: {
          // MMX registers. These alias the st0-st7 regs above, but only provide
          // 64-bit SIMD state.
-         auto &st = *reinterpret_cast< typename Op::Reg<Simd64> *> (regs.fp.xmm_space + (reg-41) * 4);
+         auto &st = *reinterpret_cast< typename Op::template Reg<Simd64> *> (regs.fp.xmm_space + (reg-41) * 4);
          regop(op, st, value);
          break;
       }