Run Verilator via aspects (#1)

Author: abrisco

MODULE.bazel

@@ -8,7 +8,7 @@ module(
 bazel_dep(name = "bazel_skylib", version = "1.8.2")
 bazel_dep(name = "platforms", version = "1.0.0")
 bazel_dep(name = "rules_cc", version = "0.2.4")
-bazel_dep(name = "verilator", version = "5.036")
+bazel_dep(name = "verilator", version = "5.036.bcr.1")
 
 register_toolchains(
     "//verilator/toolchain",

MODULE.bazel.lock

@@ -0,0 +1 @@
+workspace(name = "rules_verilog")

WORKSPACE.bazel

@@ -1,15 +1,17 @@
-"""Verilator rules.
+"""# Verilator rules.
 
-This module provides rules and aspects for working with Verilator,
-a fast Verilog/SystemVerilog simulator and linter.
+Bazel rules for [Verilator](https://verilator.org/guide/latest/index.html)
 
-Main rules:
-  - verilator_cc_library: Compiles Verilog to a C++ library
-  - verilator_lint_test: Creates a test that lints Verilog code
-  - verilator_toolchain: Defines a Verilator toolchain
+## Setup
 
-Aspects:
-  - verilator_lint_aspect: Lints Verilog code transitively
+```python
+bazel_dep(name = "rules_verilog", version = "{version}")
+
+register_toolchain(
+    # Define a custom toolchain or use the `rules_verilog` provided toolchain.
+    "@rules_verilog//verilator/toolchain",
+)
+```
 """
 
 load(

verilator/defs.bzl

@@ -1,48 +0,0 @@
-load("@rules_cc//cc:cc_test.bzl", "cc_test")
-load("//verilator:verilator_cc_library.bzl", "verilator_cc_library")
-load("//verilog:verilog_library.bzl", "verilog_library")
-
-# Basic register building block
-verilog_library(
-    name = "d_register",
-    srcs = [
-        "d_register.sv",
-    ],
-)
-
-# Shift register (depends on d_register)
-verilog_library(
-    name = "shift_register",
-    srcs = [
-        "shift_register.sv",
-    ],
-    deps = [
-        ":d_register",
-    ],
-)
-
-# Serial-to-parallel converter (depends on shift_register, which transitively depends on d_register)
-verilog_library(
-    name = "serial_to_parallel",
-    srcs = [
-        "serial_to_parallel.sv",
-    ],
-    deps = [
-        ":shift_register",
-    ],
-)
-
-verilator_cc_library(
-    name = "serial_to_parallel_verilator",
-    module = ":serial_to_parallel",
-)
-
-cc_test(
-    name = "serial_to_parallel_test",
-    srcs = [
-        "serial_to_parallel_test.cc",
-    ],
-    deps = [
-        ":serial_to_parallel_verilator",
-    ],
-)

verilator/private/tests/library_transitive_deps/BUILD.bazel

@@ -0,0 +1,9 @@
+load("//verilog:verilog_library.bzl", "verilog_library")
+
+verilog_library(
+    name = "d_register",
+    srcs = [
+        "d_register.sv",
+    ],
+    visibility = ["//verilator/private/tests/library_transitive_deps:__subpackages__"],
+)

verilator/private/tests/library_transitive_deps/d_register/BUILD.bazel

@@ -0,0 +1,29 @@
+load("@rules_cc//cc:cc_test.bzl", "cc_test")
+load("//verilator:verilator_cc_library.bzl", "verilator_cc_library")
+load("//verilog:verilog_library.bzl", "verilog_library")
+
+# Serial-to-parallel converter (depends on shift_register, which transitively depends on d_register)
+verilog_library(
+    name = "serial_to_parallel",
+    srcs = [
+        "serial_to_parallel.sv",
+    ],
+    deps = [
+        "//verilator/private/tests/library_transitive_deps/shift_register",
+    ],
+)
+
+verilator_cc_library(
+    name = "serial_to_parallel_verilator",
+    module = ":serial_to_parallel",
+)
+
+cc_test(
+    name = "serial_to_parallel_test",
+    srcs = [
+        "serial_to_parallel_test.cc",
+    ],
+    deps = [
+        ":serial_to_parallel_verilator",
+    ],
+)