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TzeWeyTzeWey
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allwinner: extend support for H5 CPU (sun50i-h5) (#22)
1 parent 79c7463 commit 8d2b28e

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3 files changed

+176
-2
lines changed

3 files changed

+176
-2
lines changed

‎allwinner/detect.go‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,14 @@ func IsA64() bool {
4444
return detection.isA64
4545
}
4646

47+
// IsH5 detects whether the host CPU is an Allwinner H5 CPU.
48+
//
49+
// It looks for the string "sun50i-h5" in /proc/device-tree/compatible.
50+
func IsH5() bool {
51+
detection.do()
52+
return detection.isH5
53+
}
54+
4755
//
4856

4957
type detectionS struct {
@@ -53,6 +61,7 @@ type detectionS struct {
5361
isR8 bool
5462
isA20 bool
5563
isA64 bool
64+
isH5 bool
5665
}
5766

5867
var detection detectionS
@@ -78,8 +87,11 @@ func (d *detectionS) do() {
7887
if strings.Contains(c, "sun7i-a20") {
7988
d.isA20 = true
8089
}
90+
if strings.Contains(c, "sun50i-h5") {
91+
d.isH5 = true
92+
}
8193
}
82-
d.isAllwinner = d.isA64 || d.isR8 || d.isA20
94+
d.isAllwinner = d.isA64 || d.isR8 || d.isA20 || d.isH5
8395

8496
if !d.isAllwinner {
8597
// The kernel in the image that comes pre-installed on the pcDuino3 Nano

‎allwinner/gpio.go‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ import (
3535
//
3636
// So make sure to read the datasheet for the exact right CPU.
3737
var (
38-
PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17 *Pin
38+
PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17, PA18, PA19, PA20, PA21 *Pin
3939
PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB20, PB21, PB22, PB23 *Pin
4040
PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PC16, PC17, PC18, PC19, PC20, PC21, PC22, PC23, PC24 *Pin
4141
PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PD16, PD17, PD18, PD19, PD20, PD21, PD22, PD23, PD24, PD25, PD26, PD27 *Pin
@@ -532,6 +532,10 @@ var cpupins = map[string]*Pin{
532532
"PA15": {group: 0, offset: 15, name: "PA15", defaultPull: gpio.Float},
533533
"PA16": {group: 0, offset: 16, name: "PA16", defaultPull: gpio.Float},
534534
"PA17": {group: 0, offset: 17, name: "PA17", defaultPull: gpio.Float},
535+
"PA18": {group: 0, offset: 18, name: "PA18", defaultPull: gpio.Float},
536+
"PA19": {group: 0, offset: 19, name: "PA19", defaultPull: gpio.Float},
537+
"PA20": {group: 0, offset: 20, name: "PA20", defaultPull: gpio.Float},
538+
"PA21": {group: 0, offset: 21, name: "PA21", defaultPull: gpio.Float},
535539
"PB0": {group: 1, offset: 0, name: "PB0", defaultPull: gpio.Float},
536540
"PB1": {group: 1, offset: 1, name: "PB1", defaultPull: gpio.Float},
537541
"PB2": {group: 1, offset: 2, name: "PB2", defaultPull: gpio.Float},
@@ -719,6 +723,10 @@ func init() {
719723
PA15 = cpupins["PA15"]
720724
PA16 = cpupins["PA16"]
721725
PA17 = cpupins["PA17"]
726+
PA18 = cpupins["PA18"]
727+
PA19 = cpupins["PA19"]
728+
PA20 = cpupins["PA20"]
729+
PA21 = cpupins["PA21"]
722730
PB0 = cpupins["PB0"]
723731
PB1 = cpupins["PB1"]
724732
PB2 = cpupins["PB2"]
@@ -1012,6 +1020,10 @@ func (d *driverGPIO) Init() (bool, error) {
10121020
if err := mapA20Pins(); err != nil {
10131021
return true, err
10141022
}
1023+
case IsH5():
1024+
if err := mapH5Pins(); err != nil {
1025+
return true, err
1026+
}
10151027
default:
10161028
return false, errors.New("unknown Allwinner CPU model")
10171029
}

‎allwinner/h5.go‎

Lines changed: 150 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,150 @@
1+
// Copyright 2022 The Periph Authors. All rights reserved.
2+
// Use of this source code is governed under the Apache License, Version 2.0
3+
// that can be found in the LICENSE file.
4+
5+
// This file contains pin mapping information that is specific to the Allwinner
6+
// H5 model.
7+
8+
package allwinner
9+
10+
import (
11+
"strings"
12+
13+
"periph.io/x/conn/v3/pin"
14+
"periph.io/x/host/v3/sysfs"
15+
)
16+
17+
// mappingH5 describes the mapping of the H5 processor gpios to their
18+
// alternate functions.
19+
//
20+
// It omits the in & out functions which are available on all gpio.
21+
//
22+
// The mapping comes from the datasheet page 55:
23+
// https://linux-sunxi.org/images/a/a3/Allwinner_H5_Manual_v1.0.pdf
24+
//
25+
// - The datasheet uses TWI instead of I2C but it is renamed here for
26+
// consistency.
27+
// - RGMII means Reduced gigabit media-independent interface.
28+
// - SDC means SDCard?
29+
// - NAND connects to a NAND flash controller.
30+
// - CSI and CCI are for video capture.
31+
var mappingH5 = map[string][5]pin.Func{
32+
"PA0": {"UART2_TX", "JTAG_MS", "", "", "PA_EINT0"},
33+
"PA1": {"UART2_RX", "JTAG_CK", "", "", "PA_EINT1"},
34+
"PA2": {"UART2_RTS", "JTAG_DO", "", "", "PA_EINT2"},
35+
"PA3": {"UART2_CTS", "JTAG_DI", "", "", "PA_EINT3"},
36+
"PA4": {"UART0_TX", "", "", "", "PA_EINT4"},
37+
"PA5": {"UART0_RX", "PWM0", "", "", "PA_EINT5"},
38+
"PA6": {"SIM0_PWREN", "PCM0_MCLK", "", "", "PA_EINT6"},
39+
"PA7": {"SIM0_CLK", "", "", "", "PA_EINT7"},
40+
"PA8": {"SIM0_DATA", "", "", "", "PA_EINT8"},
41+
"PA9": {"SIM0_RST", "", "", "", "PA_EINT9"},
42+
"PA10": {"SIM0_DET", "", "", "", "PA_EINT10"},
43+
"PA11": {"I2C0_SCK", "DI_TX", "", "", "PA_EINT11"},
44+
"PA12": {"I2C0_SDA", "DI_RX", "", "", "PA_EINT12"},
45+
"PA13": {"SPI1_CS", "UART3_TX", "", "", "PA_EINT13"},
46+
"PA14": {"SPI1_CLK", "UART3_RX", "", "", "PA_EINT14"},
47+
"PA15": {"SPI1_MOSI", "UART3_RTS", "", "", "PA_EINT15"},
48+
"PA16": {"SPI1_MISO", "UART3_CTS", "", "", "PA_EINT16"},
49+
"PA17": {"OWA_OUT", "", "", "", "PA_EINT17"},
50+
"PA18": {"PCM0_SYNC", "I2C1_SCK", "", "", "PA_EINT18"},
51+
"PA19": {"PCM0_CLK", "I2C1_SDA", "", "", "PA_EINT19"},
52+
"PA20": {"PCM0_DOUT", "SIM0_VPPEN", "", "", "PA_EINT20"},
53+
"PA21": {"PCM0_DIN", "SIM0_VPPPP", "", "", "PA_EINT21"},
54+
55+
"PC0": {"NAND_WE", "SPI0_MOSI"},
56+
"PC1": {"NAND_ALE", "SPI0_MISO", "SDC2_DS"},
57+
"PC2": {"NAND_CLE", "SPI0_CLK"},
58+
"PC3": {"NAND_CE1", "SPI0_CS"},
59+
"PC4": {"NAND_CE0", "", "SPI0_MISO"},
60+
"PC5": {"NAND_RE", "SDC2_CLK"},
61+
"PC6": {"NAND_RB0", "SDC2_CMD"},
62+
"PC7": {"NAND_RB1"},
63+
"PC8": {"NAND_DQ0", "SDC2_D0"},
64+
"PC9": {"NAND_DQ1", "SDC2_D1"},
65+
"PC10": {"NAND_DQ2", "SDC2_D2"},
66+
"PC11": {"NAND_DQ3", "SDC2_D3"},
67+
"PC12": {"NAND_DQ4", "SDC2_D4"},
68+
"PC13": {"NAND_DQ5", "SDC2_D5"},
69+
"PC14": {"NAND_DQ6", "SDC2_D6"},
70+
"PC15": {"NAND_DQ7", "SDC2_D7"},
71+
"PC16": {"NAND_DQS", "SDC2_RST"},
72+
73+
"PD0": {"RGMII_RXD3", "DI_TX", "TS2_CLK"},
74+
"PD1": {"RGMII_RXD2", "DI_RX", "TS2_ERR"},
75+
"PD2": {"RGMII_RXD1", "", "TS2_SYNC"},
76+
"PD3": {"RGMII_RXD0", "", "TS2_DVLD"},
77+
"PD4": {"RGMII_RXCK", "", "TS2_D0"},
78+
"PD5": {"RGMII_RXCTL", "", "TS2_D1"},
79+
"PD6": {"RGMII_NULL", "", "TS2_D2"},
80+
"PD7": {"RGMII_TXD3", "", "TS2_D3", "TS3_CLK"},
81+
"PD8": {"RGMII_TXD2", "", "TS2_D4", "TS3_ERR"},
82+
"PD9": {"RGMII_TXD1", "", "TS2_D5", "TS3_SYNC"},
83+
"PD10": {"RGMII_TXD0", "", "TS2_D6", "TS3_DVLD"},
84+
"PD11": {"RGMII_NULL", "", "TS2_D7", "TS3_D0"},
85+
"PD12": {"RGMII_TXCK", "", "SIM1_PWREN"},
86+
"PD13": {"RGMII_TXCTL", "", "SIM1_CLK"},
87+
"PD14": {"RGMII_NULL", "", "SIM1_DATA"},
88+
"PD15": {"RGMII_CLKIN", "", "SIM1_RST"},
89+
"PD16": {"MDC", "", "SIM1_DET"},
90+
"PD17": {"MDIO"},
91+
92+
"PE0": {"CSI_PCLK", "TS0_CLK"},
93+
"PE1": {"CSI_MCLK", "TS0_ERR"},
94+
"PE2": {"CSI_HSYNC", "TS0_SYNC"},
95+
"PE3": {"CSI_VSYNC", "TS0_DVLD"},
96+
"PE4": {"CSI_D0", "TS0_D0"},
97+
"PE5": {"CSI_D1", "TS0_D1"},
98+
"PE6": {"CSI_D2", "TS0_D2"},
99+
"PE7": {"CSI_D3", "TS0_D3", "TS1_CLK"},
100+
"PE8": {"CSI_D4", "TS0_D4", "TS1_ERR"},
101+
"PE9": {"CSI_D5", "TS0_D5", "TS1_SYNC"},
102+
"PE10": {"CSI_D6", "TS0_D6", "TS1_DVLD"},
103+
"PE11": {"CSI_D7", "TS0_D7", "TS1_D0"},
104+
"PE12": {"CSI_SCK", "I2C2_SCK"},
105+
"PE13": {"CSI_SDA", "I2C2_SDA"},
106+
"PE14": {"", "SIM1_VPPEN"},
107+
"PE15": {"", "SIM1_VPPPP"},
108+
109+
"PF0": {"SDC0_D1", "JTAG_MS", "", "", "PF_EINT0"},
110+
"PF1": {"SDC0_D0", "JTAG_DI", "", "", "PF_EINT1"},
111+
"PF2": {"SDC0_CLK", "UART0_TX", "", "", "PF_EINT2"},
112+
"PF3": {"SDC0_CMD", "JTAG_DO", "", "", "PF_EINT3"},
113+
"PF4": {"SDC0_D3", "UART0_RX", "", "", "PF_EINT4"},
114+
"PF5": {"SDC0_D2", "JTAG_CK", "", "", "PF_EINT5"},
115+
"PF6": {"", "", "", "", "PF_EINT6"},
116+
117+
"PG0": {"SDC1_CLK", "", "", "", "PG_EINT0"},
118+
"PG1": {"SDC1_CMD", "", "", "", "PG_EINT1"},
119+
"PG2": {"SDC1_D0", "", "", "", "PG_EINT2"},
120+
"PG3": {"SDC1_D1", "", "", "", "PG_EINT3"},
121+
"PG4": {"SDC1_D2", "", "", "", "PG_EINT4"},
122+
"PG5": {"SDC1_D3", "", "", "", "PG_EINT5"},
123+
"PG6": {"UART1_TX", "", "", "", "PG_EINT6"},
124+
"PG7": {"UART1_RX", "", "", "", "PG_EINT7"},
125+
"PG8": {"UART1_RTS", "", "", "", "PG_EINT8"},
126+
"PG9": {"UART1_CTS", "", "", "", "PG_EINT9"},
127+
"PG10": {"PCM1_SYNC", "", "", "", "PG_EINT10"},
128+
"PG11": {"PCM1_CLK", "", "", "", "PG_EINT11"},
129+
"PG12": {"PCM1_DOUT", "", "", "", "PG_EINT12"},
130+
"PG13": {"PCM1_DIN", "", "", "", "PG_EINT13"},
131+
}
132+
133+
// mapH5Pins uses mappingH5 to actually set the altFunc fields of all gpio
134+
// and mark them as available.
135+
//
136+
// It is called by the generic allwinner processor code if an H5 is detected.
137+
func mapH5Pins() error {
138+
for name, altFuncs := range mappingH5 {
139+
pin := cpupins[name]
140+
pin.altFunc = altFuncs
141+
pin.available = true
142+
if strings.Contains(string(altFuncs[4]), "_EINT") {
143+
pin.supportEdge = true
144+
}
145+
146+
// Initializes the sysfs corresponding pin right away.
147+
pin.sysfsPin = sysfs.Pins[pin.Number()]
148+
}
149+
return nil
150+
}

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