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sihyung-maximpetejohanson-adi
sihyung-maxim
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petejohanson-adi
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Series of AI85 Jira Ticket Fixes - I2C, UART, and GPIO (#408)
* [MSDK-1036] AI85/ME17: I2C2 RX/TX DMA added to Read/Write DMA functions. * [MSDK-1029] AI85: Removed unsupported UART HFC pins. * [MSDK-941] AI85: Added UART3 DMA Transaction Option. * [MSDK-941] GPIO: Reversed Interrupt Polarity for level-triggered mode. * [MSDK-1026] AI85: Added GPIO2 (LPGPIO) support. * [MSDK-1023] TMR: AI85: Save selected clock source frequencies for GetTime. * [MSDK-1035] Added I2C HS Mode support. * clang-format bot reformatting. * Requested changes: Removed leftover prints and renamed a few things. * I2C: ME17: Renamed HS_MODE to HIGH_SPEED. --------- Co-authored-by: sihyung-maxim <[email protected]> MSDK-Commit: ec14af9ec7c82d5014839556b0de67007e0b9d1d
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-35
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13 files changed

+145
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lines changed

‎MAX/Libraries/PeriphDrivers/Include/MAX78000/dma.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ typedef enum {
8484
MXC_DMA_REQUEST_UART2RX =
8585
MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection
8686
MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection
87+
MXC_DMA_REQUEST_UART3RX =
88+
MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection
8789
MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection
8890
MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection
8991
MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection
@@ -99,6 +101,8 @@ typedef enum {
99101
MXC_DMA_REQUEST_UART2TX =
100102
MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection
101103
MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection
104+
MXC_DMA_REQUEST_UART3TX =
105+
MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection
102106
MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection
103107
} mxc_dma_reqsel_t;
104108

‎MAX/Libraries/PeriphDrivers/Include/MAX78000/mxc_pins.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -52,14 +52,8 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart0;
5252
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow;
5353
extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable;
5454
extern const mxc_gpio_cfg_t gpio_cfg_uart1;
55-
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow;
56-
extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable;
5755
extern const mxc_gpio_cfg_t gpio_cfg_uart2;
58-
extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow;
59-
extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable;
6056
extern const mxc_gpio_cfg_t gpio_cfg_uart3;
61-
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow;
62-
extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable;
6357

6458
// Timers are only defined once, depending on package, each timer could be mapped to other pins
6559
extern const mxc_gpio_cfg_t gpio_cfg_tmr0;

‎MAX/Libraries/PeriphDrivers/Include/MAX78000/tmr.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ typedef enum {
125125
MXC_TMR_32K_CLK,
126126
/*8K and EXT clocks can only be used for Timers 4 and 5*/
127127
MXC_TMR_8K_CLK,
128+
MXC_TMR_8M_DIV8_CLK
128129
} mxc_tmr_clock_t;
129130

130131
/**
@@ -155,6 +156,23 @@ typedef void (*mxc_tmr_complete_t)(int error);
155156
*/
156157
int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins);
157158

159+
/**
160+
* @brief Save the TMRn's Clock Source Frequency.
161+
* @param tmr Pointer to timer module to save clock source frequency.
162+
* @param clksrc_freq Clock Source Frequency (Hz) value to save.
163+
*/
164+
void MXC_TMR_SetClockSourceFreq(mxc_tmr_regs_t *tmr, int clksrc_freq);
165+
166+
/**
167+
* @brief Get the saved TMRn's Clock Source Frequency.
168+
* @note This function will return an error code if the selected Timer was not
169+
* initialized.
170+
* @param tmr Pointer to timer module to retrieve respective clock source frequency.
171+
*
172+
* @return Frequency of TMRn's selected clock source (Hz). Error if bad state.
173+
*/
174+
int MXC_TMR_GetClockSourceFreq(mxc_tmr_regs_t *tmr);
175+
158176
/**
159177
* @brief Shutdown timer module clock.
160178
* @param tmr Pointer to timer module to initialize.

‎MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,10 @@ int MXC_GPIO_Init(uint32_t portmask)
5757
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1);
5858
}
5959

60+
if (portmask & 0x4) {
61+
MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO2);
62+
}
63+
6064
return MXC_GPIO_Common_Init(portmask);
6165
}
6266

@@ -70,6 +74,10 @@ int MXC_GPIO_Shutdown(uint32_t portmask)
7074
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1);
7175
}
7276

77+
if (portmask & 0x4) {
78+
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO2);
79+
}
80+
7381
return E_NO_ERROR;
7482
}
7583

@@ -83,6 +91,10 @@ int MXC_GPIO_Reset(uint32_t portmask)
8391
MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1);
8492
}
8593

94+
if (portmask & 0x4) {
95+
MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO2);
96+
}
97+
8698
return E_NO_ERROR;
8799
}
88100

‎MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
7777

7878
switch (pol) {
7979
case MXC_GPIO_INT_HIGH:
80-
gpio->intpol &= ~cfg->mask;
80+
gpio->intpol |= cfg->mask;
8181
gpio->dualedge &= ~cfg->mask;
8282
gpio->intmode &= ~cfg->mask;
8383
break;
@@ -89,7 +89,7 @@ int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol)
8989
break;
9090

9191
case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */
92-
gpio->intpol |= cfg->mask;
92+
gpio->intpol &= ~cfg->mask;
9393
gpio->dualedge &= ~cfg->mask;
9494
gpio->intmode &= ~cfg->mask;
9595
break;

‎MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me17.c‎

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,10 @@
4545
#include "i2c_reva.h"
4646

4747
/* **** Definitions **** */
48+
#define MXC_I2C_STD_MODE 100000
49+
#define MXC_I2C_FAST_SPEED 400000
4850
#define MXC_I2C_FASTPLUS_SPEED 1000000
51+
#define MXC_I2C_HIGH_SPEED 3400000
4952

5053
/* **** Variable Declaration **** */
5154
uint32_t interruptCheck = MXC_F_I2C_INTFL0_ADDR_MATCH | MXC_F_I2C_INTFL0_DNR_ERR;
@@ -121,8 +124,7 @@ int MXC_I2C_Reset(mxc_i2c_regs_t *i2c)
121124

122125
int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz)
123126
{
124-
// ME17 doesn't support high speed more
125-
if (hz > MXC_I2C_FASTPLUS_SPEED) {
127+
if (hz > MXC_I2C_HIGH_SPEED) {
126128
return E_NOT_SUPPORTED;
127129
}
128130

@@ -209,6 +211,13 @@ int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned in
209211
case 1:
210212
config.reqsel = MXC_DMA_REQUEST_I2C1RX;
211213
break;
214+
215+
case 2:
216+
config.reqsel = MXC_DMA_REQUEST_I2C2RX;
217+
break;
218+
219+
default:
220+
return E_BAD_PARAM;
212221
}
213222

214223
return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len,
@@ -241,6 +250,13 @@ int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned i
241250
case 1:
242251
config.reqsel = MXC_DMA_REQUEST_I2C1TX;
243252
break;
253+
254+
case 2:
255+
config.reqsel = MXC_DMA_REQUEST_I2C2TX;
256+
break;
257+
258+
default:
259+
return E_BAD_PARAM;
244260
}
245261

246262
return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len,

‎MAX/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -144,8 +144,8 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
144144
return E_NULL_PTR;
145145
}
146146

147-
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) {
148-
// We're going to enable high speed
147+
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED && hz <= MXC_I2C_REVA_HIGH_SPEED) {
148+
// Enable high speed mode
149149
int hsLowClks, hsHiClks;
150150

151151
// Calculate the period of SCL and set up 33% duty cycle
@@ -163,7 +163,17 @@ int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
163163
return E_BAD_PARAM;
164164
}
165165

166+
hsLowClks = (hsLowClks << MXC_F_I2C_REVA_HSCLK_LO_POS) & MXC_F_I2C_REVA_HSCLK_LO;
167+
hsHiClks = (hsHiClks << MXC_F_I2C_REVA_HSCLK_HI_POS) & MXC_F_I2C_REVA_HSCLK_HI;
168+
169+
i2c->hsclk = (hsLowClks | hsHiClks);
170+
171+
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_HS_EN;
172+
166173
hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz
174+
175+
} else if (hz > MXC_I2C_REVA_HIGH_SPEED) {
176+
return E_BAD_PARAM;
167177
}
168178

169179
// Calculate the period of SCL, 50% duty cycle

‎MAX/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
5151
#define MXC_I2C_REVA_STD_MODE 100000
5252
#define MXC_I2C_REVA_FAST_SPEED 400000
5353
#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000
54-
#define MXC_I2C_REVA_HS_MODE 3400000
54+
#define MXC_I2C_REVA_HIGH_SPEED 3400000
5555

5656
#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF
5757
#define MXC_I2C_REVA_INTFL1_MASK 0x00000007

‎MAX/Libraries/PeriphDrivers/Source/SYS/pins_ai85.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -60,10 +60,6 @@ const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_2
6060
MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE };
6161
const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13),
6262
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
63-
const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15),
64-
MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE };
65-
const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15),
66-
MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE };
6763
const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1),
6864
MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE };
6965
const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7),

‎MAX/Libraries/PeriphDrivers/Source/TMR/tmr_ai85.c‎

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,16 +56,18 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
5656

5757
clockSource = MXC_TMR_CLK1;
5858
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO);
59+
MXC_TMR_SetClockSourceFreq(tmr, ISO_FREQ);
5960
break;
6061

6162
case MXC_TMR_8M_CLK:
62-
6363
if (tmr_id > 3) {
6464
clockSource = MXC_TMR_CLK0;
6565
} else {
6666
clockSource = MXC_TMR_CLK2;
6767
}
68+
6869
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
70+
MXC_TMR_SetClockSourceFreq(tmr, IBRO_FREQ);
6971
break;
7072

7173
case MXC_TMR_32K_CLK:
@@ -78,6 +80,7 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
7880
}
7981

8082
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO);
83+
MXC_TMR_SetClockSourceFreq(tmr, ERTCO_FREQ);
8184
break;
8285

8386
case MXC_TMR_8K_CLK:
@@ -87,9 +90,23 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
8790

8891
clockSource = MXC_TMR_CLK2;
8992
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO);
93+
MXC_TMR_SetClockSourceFreq(tmr, INRO_FREQ);
94+
break;
95+
96+
// IBRO/8
97+
case MXC_TMR_8M_DIV8_CLK:
98+
if (tmr_id != 5) { // Only Timer 5 supports this clock source divide
99+
return E_NOT_SUPPORTED;
100+
}
101+
102+
clockSource = MXC_TMR_CLK1;
103+
MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO);
104+
MXC_TMR_SetClockSourceFreq(tmr, (IBRO_FREQ / 8));
90105
break;
91106

92107
default:
108+
// PCLK
109+
MXC_TMR_SetClockSourceFreq(tmr, PeripheralClock);
93110
break;
94111
}
95112

@@ -167,6 +184,16 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins)
167184
return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource);
168185
}
169186

187+
void MXC_TMR_SetClockSourceFreq(mxc_tmr_regs_t *tmr, int clksrc_freq)
188+
{
189+
MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, clksrc_freq);
190+
}
191+
192+
int MXC_TMR_GetClockSourceFreq(mxc_tmr_regs_t *tmr)
193+
{
194+
return MXC_TMR_RevB_GetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr);
195+
}
196+
170197
void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr)
171198
{
172199
MXC_ASSERT(MXC_TMR_GET_IDX(tmr) >= 0);

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