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| 1 | +/** |
| 2 | + * @file sfcc_regs.h |
| 3 | + * @brief Registers, Bit Masks and Bit Positions for the SFCC Peripheral Module. |
| 4 | + * @note This file is @generated. |
| 5 | + */ |
| 6 | + |
| 7 | +/****************************************************************************** |
| 8 | + * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. |
| 9 | + * |
| 10 | + * Permission is hereby granted, free of charge, to any person obtaining a |
| 11 | + * copy of this software and associated documentation files (the "Software"), |
| 12 | + * to deal in the Software without restriction, including without limitation |
| 13 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 14 | + * and/or sell copies of the Software, and to permit persons to whom the |
| 15 | + * Software is furnished to do so, subject to the following conditions: |
| 16 | + * |
| 17 | + * The above copyright notice and this permission notice shall be included |
| 18 | + * in all copies or substantial portions of the Software. |
| 19 | + * |
| 20 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 21 | + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 22 | + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 23 | + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| 24 | + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 25 | + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 26 | + * OTHER DEALINGS IN THE SOFTWARE. |
| 27 | + * |
| 28 | + * Except as contained in this notice, the name of Maxim Integrated |
| 29 | + * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| 30 | + * Products, Inc. Branding Policy. |
| 31 | + * |
| 32 | + * The mere transfer of this software does not imply any licenses |
| 33 | + * of trade secrets, proprietary technology, copyrights, patents, |
| 34 | + * trademarks, maskwork rights, or any other form of intellectual |
| 35 | + * property whatsoever. Maxim Integrated Products, Inc. retains all |
| 36 | + * ownership rights. |
| 37 | + * |
| 38 | + ******************************************************************************/ |
| 39 | + |
| 40 | +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SFCC_REGS_H_ |
| 41 | +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SFCC_REGS_H_ |
| 42 | + |
| 43 | +/* **** Includes **** */ |
| 44 | +#include <stdint.h> |
| 45 | + |
| 46 | +#ifdef __cplusplus |
| 47 | +extern "C" { |
| 48 | +#endif |
| 49 | + |
| 50 | +#if defined (__ICCARM__) |
| 51 | + #pragma system_include |
| 52 | +#endif |
| 53 | + |
| 54 | +#if defined (__CC_ARM) |
| 55 | + #pragma anon_unions |
| 56 | +#endif |
| 57 | +/// @cond |
| 58 | +/* |
| 59 | + If types are not defined elsewhere (CMSIS) define them here |
| 60 | +*/ |
| 61 | +#ifndef __IO |
| 62 | +#define __IO volatile |
| 63 | +#endif |
| 64 | +#ifndef __I |
| 65 | +#define __I volatile const |
| 66 | +#endif |
| 67 | +#ifndef __O |
| 68 | +#define __O volatile |
| 69 | +#endif |
| 70 | +#ifndef __R |
| 71 | +#define __R volatile const |
| 72 | +#endif |
| 73 | +/// @endcond |
| 74 | + |
| 75 | +/* **** Definitions **** */ |
| 76 | + |
| 77 | +/** |
| 78 | + * @ingroup sfcc |
| 79 | + * @defgroup sfcc_registers SFCC_Registers |
| 80 | + * @brief Registers, Bit Masks and Bit Positions for the SFCC Peripheral Module. |
| 81 | + * @details SPIXF Cache Controller Registers |
| 82 | + */ |
| 83 | + |
| 84 | +/** |
| 85 | + * @ingroup sfcc_registers |
| 86 | + * Structure type to access the SFCC Registers. |
| 87 | + */ |
| 88 | +typedef struct { |
| 89 | + __I uint32_t info; /**< <tt>\b 0x0000:</tt> SFCC INFO Register */ |
| 90 | + __I uint32_t sz; /**< <tt>\b 0x0004:</tt> SFCC SZ Register */ |
| 91 | + __R uint32_t rsv_0x8_0xff[62]; |
| 92 | + __IO uint32_t ctrl; /**< <tt>\b 0x0100:</tt> SFCC CTRL Register */ |
| 93 | + __R uint32_t rsv_0x104_0x6ff[383]; |
| 94 | + __IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> SFCC INVALIDATE Register */ |
| 95 | +} mxc_sfcc_regs_t; |
| 96 | + |
| 97 | +/* Register offsets for module SFCC */ |
| 98 | +/** |
| 99 | + * @ingroup sfcc_registers |
| 100 | + * @defgroup SFCC_Register_Offsets Register Offsets |
| 101 | + * @brief SFCC Peripheral Register Offsets from the SFCC Base Peripheral Address. |
| 102 | + * @{ |
| 103 | + */ |
| 104 | +#define MXC_R_SFCC_INFO ((uint32_t)0x00000000UL) /**< Offset from SFCC Base Address: <tt> 0x0000</tt> */ |
| 105 | +#define MXC_R_SFCC_SZ ((uint32_t)0x00000004UL) /**< Offset from SFCC Base Address: <tt> 0x0004</tt> */ |
| 106 | +#define MXC_R_SFCC_CTRL ((uint32_t)0x00000100UL) /**< Offset from SFCC Base Address: <tt> 0x0100</tt> */ |
| 107 | +#define MXC_R_SFCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SFCC Base Address: <tt> 0x0700</tt> */ |
| 108 | +/**@} end of group sfcc_registers */ |
| 109 | + |
| 110 | +/** |
| 111 | + * @ingroup sfcc_registers |
| 112 | + * @defgroup SFCC_INFO SFCC_INFO |
| 113 | + * @brief Cache ID Register. |
| 114 | + * @{ |
| 115 | + */ |
| 116 | +#define MXC_F_SFCC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ |
| 117 | +#define MXC_F_SFCC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_SFCC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ |
| 118 | + |
| 119 | +#define MXC_F_SFCC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ |
| 120 | +#define MXC_F_SFCC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_SFCC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ |
| 121 | + |
| 122 | +#define MXC_F_SFCC_INFO_ID_POS 10 /**< INFO_ID Position */ |
| 123 | +#define MXC_F_SFCC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_SFCC_INFO_ID_POS)) /**< INFO_ID Mask */ |
| 124 | + |
| 125 | +/**@} end of group SFCC_INFO_Register */ |
| 126 | + |
| 127 | +/** |
| 128 | + * @ingroup sfcc_registers |
| 129 | + * @defgroup SFCC_SZ SFCC_SZ |
| 130 | + * @brief Memory Configuration Register. |
| 131 | + * @{ |
| 132 | + */ |
| 133 | +#define MXC_F_SFCC_SZ_CCH_POS 0 /**< SZ_CCH Position */ |
| 134 | +#define MXC_F_SFCC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_SFCC_SZ_CCH_POS)) /**< SZ_CCH Mask */ |
| 135 | + |
| 136 | +#define MXC_F_SFCC_SZ_MEM_POS 16 /**< SZ_MEM Position */ |
| 137 | +#define MXC_F_SFCC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_SFCC_SZ_MEM_POS)) /**< SZ_MEM Mask */ |
| 138 | + |
| 139 | +/**@} end of group SFCC_SZ_Register */ |
| 140 | + |
| 141 | +/** |
| 142 | + * @ingroup sfcc_registers |
| 143 | + * @defgroup SFCC_CTRL SFCC_CTRL |
| 144 | + * @brief Cache Control and Status Register. |
| 145 | + * @{ |
| 146 | + */ |
| 147 | +#define MXC_F_SFCC_CTRL_EN_POS 0 /**< CTRL_EN Position */ |
| 148 | +#define MXC_F_SFCC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_SFCC_CTRL_EN_POS)) /**< CTRL_EN Mask */ |
| 149 | + |
| 150 | +#define MXC_F_SFCC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ |
| 151 | +#define MXC_F_SFCC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_SFCC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ |
| 152 | + |
| 153 | +/**@} end of group SFCC_CTRL_Register */ |
| 154 | + |
| 155 | +/** |
| 156 | + * @ingroup sfcc_registers |
| 157 | + * @defgroup SFCC_INVALIDATE SFCC_INVALIDATE |
| 158 | + * @brief Invalidate All Registers. |
| 159 | + * @{ |
| 160 | + */ |
| 161 | +#define MXC_F_SFCC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ |
| 162 | +#define MXC_F_SFCC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_SFCC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ |
| 163 | + |
| 164 | +/**@} end of group SFCC_INVALIDATE_Register */ |
| 165 | + |
| 166 | +#ifdef __cplusplus |
| 167 | +} |
| 168 | +#endif |
| 169 | + |
| 170 | +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_SFCC_REGS_H_ |
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